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US 6,959,357 B2Granted
Integrated circuit and method of controlling same
AssigneeFuji Photo Film Co., Ltd.
InventorKaoru Adachi
Life of this patent
Estimating the term…
Abstract
Bus-connected circuits are made to operate stably and at high speed. A cache memory for high-speed access and a DRAM for low-speed access are connected to a CPU by an address bus, control bus and data transfer bus. A switch is provided in the bus at a point between the cache memory and DRAM and the switch is opened at the time of high-speed access. Since bus length is essentially shortened at such time, the cache memory can be accessed stably at high speed. When the DRAM is accessed, the switch is closed.
Claims5
A bus architecture, comprising:
- first, second, and third bus portions;
- a first switch configured to enable/disable a connection between the first and second bus portions;
- and
- a second switch configured to enable/disable a connection between the second and third bus portions,
- wherein each of the first, second, and third bus portion operate based on a bus start signal and a data complete signal such that data transfer on the bus starts when the bus start signal is enabled and the data complete signal is disabled,
- wherein a delay between enabling of the bus start signal and disabling of the data complete signal varies based on enabled/disabled states of the first and second switches.
3 more elements
Dependencies are inferred from the claim text.