Effective bus utilization using multiple bus interface circuits and arbitration logic circuit
AssigneesSony Corporation, Sony Electronics Inc.
InventorHidekazu Watanabe
Life of this patent
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Abstract
In one embodiment of the present invention, a bus controller is used in a multi-bus system having first and second buses. The bus controller includes first and second bus interface circuits, a processor interface circuit, and an arbitration logic circuit. The first and second bus interface circuits interface to the first and second buses, respectively. The first bus is accessible to a first processor. The processor interface circuit interfaces to a second processor. The arbitration logic circuit is coupled to the first and second bus interface circuits and the processor interface circuit to arbitrate access requests from the first and second processors.
Claims27
An apparatus comprising:
- first and second bus interface circuits to interface to first and second buses, respectively, the first bus being accessible to a first processor;
- a processor interface circuit to interface to a second processor, the second processor having accessibility to the first and second buses;
- and
- an arbitration logic circuit coupled to the first and second bus interface circuits and the processor interface circuit to arbitrate access request from the first and second processor;
- wherein the arbitration logic circuit disables the first bus interface circuit when the second processor requests access to the second bus.
A method comprising:
- interfacing to first and second buses by first and second interface circuits, respectively, the first bus being accessible to a first processor;
- interfacing to a second processor, the second processor having accessibility to the first and second buses;
- and
- arbitrating access requests from the first and second processors;
- wherein arbitrating access requests comprises disabling the first bus interface circuit when access request to the second bus from the second processor is granted.
A system comprising:
- first and second buses;
- first and second processors, the first processor being coupled to the first bus;
- a bus controller coupled to the first and second buses to control bus access from the first and second processors, the bus controller comprising:
- first and second bus interface circuits to interface to the first and second buses, respectively,
- a processor interface circuit to interface to the second processor, the second processor having accessibility to the first and second buses, and
- an arbitration logic circuit coupled to the first and second bus interface circuits and the processor interface circuit to arbitrate access request from the first and second processor;
- wherein the arbitration logic circuit disables the first bus interface circuit when the second processor requests access to the second bus.
Dependencies are inferred from the claim text.