System and method for allowing non-trusted processors to interrupt a processor safely
AssigneeHewlett-Packard Development Company, L.P.
InventorKent A. Dickey
Life of this patent
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Abstract
The present invention provides for a method and system for allowing non-trusted partitions in large scale computer system to safely interrupt a processor without the risk of corruption or loss of interconnect bandwidth, and without the need for inefficient hardwiring. In operation code preferably located outside of the central processor, interrupts coming from outside the partition into specific addresses for determination of allowability into the partition.
Claims14
A method for allowing a processor located outside a partition to safely interrupt a processor located within a partition comprising the steps of:
- receiving a transaction, directed to a target processor within said partition, with chipset logic that is separate from said target processor;
- determining if said transaction is from another processor within said partition or from said processor located outside said partition;
- allowing a transaction to proceed to said target processor if said transaction is determined to be from said other in-partition processor;
- if said transaction is determined to be from said out-of-partition processor, evaluating said transaction to determine whether said transaction is of a particular type;
- if said transaction has been determined to be of said particular type, substantively altering said out-of-partition transaction;
- and
- allowing said altered transaction to proceed to the processor.
A module for allowing a processor located outside a partition to safely communicate interrupts to a target processor located within said partition, said module comprising:
- a chipset that receives for receiving a transaction directed to said in-partition processor, and that is physically separate from said target processor;
- a determination module that determines a location of said source processor;
- a transaction module that drives a transaction from a source processor determined to be within said partition to said target processor;
- an evaluation module that evaluates a transaction from a source processor determined to be outside said partition, and determines if said out-of-partition transaction is an interrupt;
- a modification module that structurally alters out-of-partition interrupts;
- and
- an allowance module that drives altered out-of partition interrupts to said target processor.
Computer readable code, stored on a computer readable medium, said code comprising:
- code for determining a source of a transaction directed to a target processor, wherein said target processor is located within a computer system partition, and wherein said source determining code determines if said source is located inside or outside said partition;
- code for determining a nature of a transaction determined to have an out-of-partition source, wherein said nature determining code determines if said out-of-partition transaction is an interrupt;
- code for performing at least one bitwise operation on said out-of-partition interrupt that structurally alters said out-of-partition interrupt;
- and
- code for driving said alleged out-of-partition interrupt to said target processor.
Dependencies are inferred from the claim text.