Method and apparatus for increasing processing performance of pipelined averaging filters

A pipelined averaging filter comprising:

• at least one subtractor section having a plurality of adder logic units;
• and
• at least one adder section having a plurality of adder logic units,
• wherein the at least one adder section includes a one delay feedback for each of the plurality of adder logic units and comprises a plurality of bit segments that are different from one another.

A pipelined averaging filter comprising:

• at least one subtractor section having a plurality of adder logic units;
• and
• at least one adder section having a plurality of adder logic units,
• wherein the averaging filter includes a delay enable signal output for each of the plurality of adder logic units of the at least one adder section.

A pipelined processor comprising:

• at least a first processor section having a plurality of adder logic units;
• and
• at least a second processor section having a plurality of adder logic units, each adder logic unit of the at least first processor section being associated with a corresponding adder logic unit of the at least second processor section,
• wherein the at least a first processor section and the at least a second processor section are interleaved with one another such that each adder logic unit of the at least first processor section is coupled to the corresponding adder logic unit of the at least second processor section to thereby receive therefrom as a direct input the output of said corresponding adder logic unit of the at least second processor section.

A method of pipelined processing an n-bit word, the method comprising:

• dividing the n-bit word into a plurality of bit segments;
• generating a delay enable signal for each of the plurality of bit segments;
• processing the plurality of bit segments;
• and
• applying the delay enable signal to each of the processed plurality of bit segments to assemble the output of the pipelined processing.

A pipelined processor for an n-bit word, the processor comprising:

• means for dividing the n-bit word into a plurality of bit segments;
• means for generating a delay enable signal for each of the plurality of bit segments;
• means for processing the plurality of bit segments;
• and
• means for applying the delay enable signal to each of the processed plurality of bit segments to assemble the output of the pipelined processor.