Method and system for generating an ATPG model of a memory from behavioral descriptions

A content addressable memory model usable for computer simulation and automatic test pattern generation, the content addressable memory model comprising:

• a memory primitive including an output port;
• a compare port primitive including a data port for coupling to the output port of the memory primitive, a data bus port, and an output port;
• a data bus primitive including an output port for coupling to the data bus port of the compare port primitive;
• a plurality of memory output primitives, each memory output primitive including an input port for coupling to the output port of the compare port primitive and an output port;
• and
• an address bus primitive including input ports for coupling the output ports of a set of the memory output primitives.

A combined content addressable memory (CAM) and random access memory (RAM) model usable for computer simulation and automatic test pattern generation, the combined CAM and RAM model comprising:

• a first memory primitive including an output port;
• a data bus primitive including an output port;
• a compare port primitive for coupling to the memory primitive and the data bus primitive, the compare port primitive comprising;
• a compare enable port;
• a data bus port for coupling to the output port of the data bus primitive;
• a data port for coupling to the output port of the first memory primitive;
• and
• an output port;
• a first plurality of memory output primitives, each memory output primitive including an output port and an input port for coupling to the output port of the compare port primitive;
• an address bus primitive including an output port and input ports for coupling to output ports of a first subset of the first plurality of memory output primitives;
• a second memory primitive including an output port;
• a read data port primitive including a first input port for coupling to the output port of the second memory primitive, a second input port for coupling to an output port of the address bus primitive, and a third input port for coupling to the output ports of a second subset of the plurality of memory output primitives;
• and
• a second plurality of memory output primitives, each memory output primitive including an input port for coupling to an output port of the read data port primitive.