Clock recovery PLL
AssigneeZarlink Semiconductor Inc.
InventorsMenno Spijker, George Jeffrey
Life of this patent
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Abstract
A multimode clock recovery circuit for providing constant bit rate services in a cell relay network has an embedded digital phase locked loop including an input circuit capable of generating a phase signal from at least two types of input signal. The phase signal controlling the output of the phase locked loop generates clock signals for the constant bit rate services.
Claims18
A multimode clock recovery circuit for use in the provision of constant bit rate services in a cell relay network, comprising:
- a digital phase locked loop including a digital controlled oscillator for generating an output signal, a loop filter responsive to a phase signal to control said digital controlled oscillator, and a phase detector having multiple inputs for receiving different types of input signal;
- said phase detector comparing an input signal applied to any of said multiple inputs with said output signal to develop said phase signal;
- a local Synchronous Residual Time Stamps (SRTS) generator for generating time stamps from said output signal connected to one of said multiple inputs of said phase detector;
- said phase detector in a SRTS mode developing said phase signal from said locally generated time stamps and time stamps received over said cell relay network;
- another of said multiple inputs of said phase detector being adapted to receive a line rate clock signal;
- said phase detector in a line rate mode developing said phase signal from said line rate clock signal and said output signal;
- and
- a receive buffer for receiving incoming cells that in an adaptive mode develops said phase signal from a state of said receive buffer and applies said phase signal developed by said receive buffer to said loop filter to control said digital controlled oscillator.
A multimode clock recovery circuit for use in providing constant bit rate scrvices in a cell relay network, comprising a phase detector having multiple inputs, a loop filter receiving the output of said phase detector, a digital controlled oscillator receiving the output of said loop filter, a jitter reduction circuit receiving the output of said digital controlled oscillator, a divider receiving the output of said jitter reduction circuit, and a local Synchronous Residual Time Stamps (SRTS) generator in a feedback loop connected to one of said multiple inputs of said phase detector, said local SRTS generator generating local time stamps derived from the output of said digital controlled oscillator, and said phase detector developing a phase signal for controlling said digital controlied oscillator from said local time stamps and time stamps received from said cell relay network, and wherein said local SRTS generator includes a wrap-around counter, said phase signal is developed from the difference between the time stamps received from said local SRTS generator and said time stamps received over said cell relay network, and said phase detector includes a weighted non-wrap around up/down counter having an output that is added to said difference.
A phase detector for recovering clock signals from received time stamps in a cell relay network providing constant bit rate services, comprising a first input for receiving a remote time stamp signal, a second input for receiving a locally generated time stamp signal, comparators for comparing the current time stamps of said first input and said second input with the previous time stamps of said first input and second input to generate, a weighted non-wrap around up/down counter receiving the outputs of said respective comparators, a subtractor for deriving the difference between said remote time stamp signal and said locally generated time stamp and an accumulator for adding the output of said subtractor to the output of said weighted non-wrap around up/down counter to generate a phase output signal for controlling a digital controlled oscillator.
Dependencies are inferred from the claim text.