Variable delay line

A method of operation of a delay lock loop comprising:

• comparing a phase of a first clock signal with a phase of a second clock signal to generate a first control signal;
• delaying the first clock signal to generate a first delayed clock signal;
• comparing a phase of the first delayed clock signal with the phase of the second clock signal to generate a second control signal;
• shifting a phase of the first clock signal in response to the first control signal and the second control signal;
• delaying the second clock signal to generate a second delayed clock signal;
• comparing a phase of the second delayed clock signal with the phase of the first clock signal a first amount and a second amount respectively;
• and
• shifting the phase of the first clock signal a third amount in response to the third control signal.

A method of setting a delay value in a delay lock loop comprising:

• delaying a first signal in a variable delay line to generate a second signal;
• comparing a phase of the first signal with a phase of the second signal to generate a first control signal;
• delaying the first signal by a first substantially fixed amount to generate a third signal;
• comparing the phase of the second signal with a phase of the third signal to generate a second control signal;
• responsive to the first control signal, adjusting the variable delay line by a first delay amount;
• and
• responsive to the second control signal, adjusting the variable delay line by a second delay amount, the second delay amount being greater than the first delay amount.

A method of aligning a phase of a first signal external to a device and a phase of a second signal internal to the device comprising:

• receiving the first signal into the device, and subjecting the first signal to a device boundary delay to produce an internal first signal;
• delaying the internal first signal in a variable delay line to generate the second signal, the variable delay line having a fine adjustment control and a coarse adjustment control;
• delaying the second signal a substantially fixed amount to produce a delayed second signal;
• comparing the internal first signal with the second signal, and responsive thereto, driving the fine adjustment control;
• and
• comparing the internal first signal with the delayed second signal, and responsive thereto, driving the coarse adjustment control.

In a memory device having data output drivers configured to drive data signals external to the memory device, a method of aligning the data signals with an external clock signal comprising:

• receiving the external clock signal;
• delaying the external clock signal in a variable delay line having a variable delay associated therewith, to produce an internal clock signal;
• generating a first phase difference between the external clock signal and the internal clock signal;
• comparing the first phase difference to a threshold;
• when the first phase difference is above the threshold, changing the variable delay a first delay amount;
• when the first phase difference is not above the threshold, changing the variable delay a second delay amount, the second delay amount being less than the first delay amount;
• delaying the internal clock signal to produce a delayed internal clock signal;
• generating a second phase difference between the external clock signal and the delayed internal clock signal;
• changing the variable delay a third delay amount;
• and
• driving a control input of the data output drivers with the internal clock.

In a memory device having data output drivers configured to drive data signals external to the memory device, a method of aligning the data signals with an external clock signal comprising:

• receiving the external clock signal;
• delaying the external clock signal in a variable delay line having a variable delay associated therewith, to produce an internal clock signal;
• generating a phase difference between the external clock signal and the internal clock signal;
• comparing the phase difference to a threshold;
• when the phase difference is above the threshold, changing the variable delay a first delay amount;
• when the phase difference is not above the threshold, changing the variable delay a second delay amount, the second delay amount being less than the first delay amount;
• driving a control input of the data output drivers with the internal clock;
• wherein generating a phase difference and comparing the phase difference comprise:
• delaying the external clock signal by an amount substantially equal to the threshold to generate a delayed external clock signal;
• and
• comparing the delayed external clock signal to the internal clock signal.

In a delay line having a variable delay, a method of changing the variable delay comprising:

• comparing a phase of a signal input to the delay line with a phase of a signal output from the delay line to produce a first phase difference;
• when the first phase difference is larger than a first threshold, adjusting the variable delay by a first delay amount;
• when the first phase difference is not larger than the first threshold and is larger than a second threshold, adjusting the variable delay by a second delay amount, the second delay amount being less than the first delay amount;
• delaying the signal input to the delay line to produce a third signal;
• comparing the phase of the signal output from the delay line to the third signal to produce a third delay amount;
• and
• adjusting the variable delay by the third delay amount.

A phase detector comprising:

• a first input node, a second input node, a first output node, and a second output node;
• a first phase comparator coupled to receive an external clock signal from the first input node and coupled to receive an internal clock signal from the second input node and coupled to produce a fine adjustment signal on the first output node;
• a first delay line coupled to receive the external clock signal from the first input node and coupled to produce a delayed external clock signal;
• a second phase comparator coupled to receive the delayed external clock signal from the first delay line and coupled to receive the internal clock signal from the second input node and coupled to produce a coarse increase adjustment signal on the second output node;
• a second delay line coupled to receive the internal clock signal from the second input node and coupled to produce a delayed internal clock signal;
• and
• a third phase comparator coupled to receive the delayed internal clock signal from the second delay line and coupled to receive the external clock signal from the first input node, and coupled to produce a coarse decrease adjustment signal on the second output node.

A phase detector comprising:

• a first input node, a second input node, a first output node, and a second output node;
• a first phase comparator coupled between the first input node, the second input node, and the first output node;
• a first delay line coupled to the first input node;
• a second phase comparator coupled between the first delay line, the second input node, and the second output node;
• a third output node;
• a second delay line coupled to the second input node;
• and
• a third phase comparator coupled between the first input node, the second delay line, and the third output node.

A phase detector comprising:

• a first input node, a second input node, a first output node, and a second output node;
• a first phase comparator coupled to receive clock signals from the first input node and, the second input node, and for producing a fine increase adjustment signal on the first output node and for producing a fine decrease adjustment signal on the second output node;
• a first delay line coupled to the first input node and coupled to produce a first delayed signal;
• a second delay line coupled to the second input node and coupled to produce a second delayed signal;
• a second phase comparator coupled to receive the first delayed signal from the first delay line and coupled to the second input node for producing a coarse increase adjustment signal on a third output node;
• and
• a third phase comparator coupled to receive the second delayed signal from the second delay line and coupled to the first input node for producing a coarse decrease adjustment signal on a fourth output node.

A delay lock loop comprising:

• a variable delay line including a plurality of delay cells and an input connected to receive an external signal;
• a shift register having a plurality of storage elements, each of the plurality of storage elements corresponding to one of the plurality of delay cells, the plurality of storage elements being arranged in a plurality of blocks of storage elements, the shift register having a fine control input node, and a coarse control input node;
• a phase detector having a fine adjustment output node coupled to the fine control input node, and having a coarse adjustment output node coupled to the coarse control input node the phase detector further comprising:
• a first phase comparator operable for comparing a phase of the external signal to a phase of a variable delay signal output from the variable delay line and producing therefrom a first delay amount signal on the fine adjustment output node;
• and
• a second phase comparator operable for comparing a phase of a delayed version of the external signal to the variable delay signal output from the variable delay line and producing therefrom a second delay amount signal on the coarse adjustment output node.

A variable delay line comprising:

• a coarse adjustment portion comprising a first plurality of delay cells and a first shift register;
• a fine adjustment portion comprising a second plurality of delay cells and a second shift register, wherein each of the first plurality of delay cells has a delay value larger than that of each of the second plurality of delay cells;
• a first phase comparator operable for comparing a phase of an external clock signal to a phase of a internal clock signal output from the variable delay line and producing therefrom a first delay amount signal connected to control the fine adjustment portion;
• and
• a second phase comparator operable for comparing a phase of a delayed version of the external clock signal and a phase of internal clock signal and producing therefrom a second delay amount signal connected to control the coarse adjustment portion.

An integrated circuit comprising:

• a variable delay line having an input node, an output node, a fine adjustment input node, and a coarse adjustment input node;
• a first phase detector configured to compare a signal on the input node with a signal on the output node and drive signals onto the fine adjustment input node;
• and
• a second phase detector configured to compare the signal on the output node with a delayed version of the signal on the input node and drive signals onto the coarse adjustment input node.

A processing system comprising:

• a processor;
• and
• a memory having a delay lock loop comprising:
• a variable delay line including a plurality of delay cells and an input connected to receive an external signal;
• a shift register having a plurality of storage elements, each of the plurality of storage elements corresponding to one of the plurality of delay cells, the plurality of storage elements being arranged in a plurality of blocks of storage elements, the shift register having a fine control input node, and a coarse control input node;
• a phase detector having a fine adjustment output node coupled to the fine control input node, and having a coarse adjustment output node coupled to the coarse control input node node the phase detector further comprising:
• a first phase comparator operable for comparing a phase of the external signal to a phase of a variable delay signal output from the variable delay line and producing therefrom a first delay amount signal on the fine adjustment output node;
• and
• a second phase comparator operable for comparing a phase of a delayed version of the external signal to the variable delay signal output from the variable delay line and producing therefrom a second delay amount signal on the coarse adjustment output node.

A processing system comprising:

• a processor;
• and
• a memory having a delay lock loop that includes a phase detector comprising:
• a first input node, a second input node, a first output node, and a second output node;
• a first phase comparator coupled between the first input node, the second input node, and the first output node;
• a first delay line coupled to the first input node;
• and
• a second phase comparator coupled between the first delay line, the second input node, and the second output node;
• a third output node;
• a second delay line coupled to the second input node;
• and
• a third phase comparator coupled between the first input node, the second delay line, and the third output node.

A processing system comprising:

• a processor;
• and
• a memory having a delay lock loop that includes a variable delay line comprising:
• a coarse adjustment portion comprising a first plurality of delay cells and a first shift register;
• a fine adjustment portion comprising a second plurality of delay cells and a second shift register, wherein each of the first plurality of delay cells has a delay value larger than that of each of the second plurality of delay cells;
• a first phase comparator operable for comparing a phase of an external clock signal to a phase of a internal clock signal output from the variable delay line and producing therefrom a first delay amount signal connected to control the fine adjustment portion;
• and
• a second phase comparator operable for comparing a phase of a delayed version of the external clock signal and a phase of internal clock signal and producing therefrom a second delay amount signal connected to control the coarse adjustment portion.