Phase comparator circuit

A phase comparison circuit, comprising:

• a data discriminator to which a data signal is input for discriminating the data signal using a clock signal:
• a detector for outputting a phase-difference signal representing a phase difference between the data signal and the clock signal:
• a clock generator which generates the clock signal synchronized to the data signal based on the phase-difference signal:
• an erroneous-synchronization phase detector for detecting whether the phase difference between the data signal and the clock signal resides within a range of phases for which there is a possibility of erroneous synchronization;
• and
• an output fixing unit for (a) outputting the phase-difference signal if the phase difference between the data signal and the clock signal falls outside said range of phases, (b) outputting a first set value if the phase difference resides within said range of phases and is varying in an increasing direction, and (c) outputting a second value if the phase difference resides within said range of phases and is varying in a decreasing direction,
• wherein the possibility of erroneous synchronizations occurs where the data signal duty cycle shifts from 100% and a data signal that has been acted upon by a circuit that compensates for duty is adopted as said data signal.

A phase comparison circuit, comprising:

• a data discriminator to which a data signal is input for discriminating the data sigal using a clock signal:
• a detector for outputting a phase-difference signal representing a phase difference between the data signal and the clock signal:
• a clock generator which generates the clock signal synchronized to the data signal based on the phase-difference signal:
• an erroneous-synchronization phase detector for detecting whether the phase difference between the data signal and the clock signal resides within a rage of phases for which there is a possibility of erroneous synchronization;
• and
• an output fixing unit for (a) outputting the phase-difference signal if the phase difference between the data signal and the clock signal falls outside said range of phases, (b) outputting a first set value if the phase difference resides within said range of phases and is varying in an increasing direction, and (c) outputting a second value if the phase difference resides with said range of phases and is varying in a decreasing direction,
• wherein the possibility of erroneous synchronizations occurs where the data signal duty cycle shifts from 100%.