Post-correlation interpolation for delay locked loops

A CDMA receiver, comprising:

• an analog processing circuit for removing a carrier frequency from a received CDMA signal and for sampling the received CDMA signal at a predetermined sampling rate to produce corresponding CDMA chip samples;
• an interpolator for receiving the CDMA chip samples from the analog processing circuit and for generating time shifted chip samples from the CDMA chip samples;
• first and second correlators for extracting, respectively, ontime control symbol samples and data symbol samples from one of the CDMA chip samples and the time shifted chip samples;
• a third correlator for extracting first non-ontime control symbol samples from one of the CDMA chip samples and the time shifted chip samples;
• and
• wherein the first non-ontime control symbol samples and the ontime control symbol samples are used for extracting second non-ontime symbol samples for delay locked loop processing.

A method of processing samples for delay locked loop processing, comprising:

• interpolating between received samples to generate time shifted samples;
• extracting ontime control symbol samples from one of the received samples and the time shifted samples;
• extracting first non-ontime control symbol samples from one of the received samples and the time shifted samples;
• and
• subsequently extracting second non-ontime symbol samples based on the first non-ontime control symbol samples and the ontime control symbol samples.