Back to results
US 6,958,948 B2Granted
Semiconductor device having a data latching or storing function
AssigneeTexas Instruments Incorporated
InventorAtsushi Shiraishi
Life of this patent
Estimating the term…
Abstract
The current consumed by latching data and during standby are significantly decreased in order to realize reduced power consumption. In this memory cell, source voltages VRET and VDD are supplied to latch circuit 10 and output circuit 32 from different systems. Latch circuit 10 can be separated from a peripheral circuit by NMOS transistor 20 and transmission gate 24. MOS transistors 12, 14, 16, and 18, which constitute latch circuit 10 and MOS transistors 20, 26, and 28, which constitute the switch circuit, are configured using low-leakage MOS transistors with leakage current significantly lower than those of standard MOS transistors used to configure the peripheral circuit including output circuit 32.
Claims21
A semiconductor device comprising:
- a latch circuit including at least one MOS transistor for latching one bit of data electrically in the form of a voltage;
- a peripheral circuit including at least one MOS transistor for exchanging data with said latch circuit;
- a switch circuit including at least one MOS transistor for connecting and disconnecting said latch circuit to and from said peripheral circuit;
- a first source voltage supply part for supplying a first source voltage to said peripheral circuit;
- a second source voltage supply part for supplying a second source voltage to the latch circuit;
- a first controller part for controlling the turning on and off of the first source voltage supply part independently of the second source voltage supply part;
- and
- a second controller part for controlling the turning on and off of the switch circuit sequentially with the turning on and off of the first source voltage supply part, wherein the MOS transistors included in the latch circuit and the switch circuit are configured using a low-leakage MOS transistor with a lower leakage current than that of the MOS transistor included in the peripheral circuit.
5 more elements
A semiconductor device comprising:
- a latch circuit including at least one MOS transistor for latching one bit of data electrically in the form of a voltage;
- a write circuit including at least one MOS transistor for writing data to the latch circuit;
- a first switch circuit including at least one MOS transistor for connecting and disconnecting the latch circuit to and from the write circuit;
- a read circuit including at least one MOS transistor for reading data from the latch circuit;
- a second switch circuit including at least one MOS transistor for connecting and disconnecting the latch circuit to and from the read circuit;
- a first source voltage supply part for supplying a first source voltage to the write circuit and the read circuit;
- a second source voltage supply part for supplying a second source voltage to the latch circuit;
- a first controller part for controlling the turning on and off of the first source voltage supply part independently of the second source voltage supply part;
- and
- a second controller part for controlling the turning on and off of the first and the second switch circuits sequentially with the turning on and off of the first source voltage supply part, wherein the MOS transistors included in the latch circuit and the first and the second switch circuit are configured using a low-leakage MOS transistor with a lower leakage current than those of the MOS transistors included in the write circuit and the read circuit.
7 more elements
A semiconductor device comprising a memory cell which comprises:
- a latch circuit including first and second data storage nodes for latching one bit of data electrically in the form of two types of voltages with opposite logic levels and at least one MOS transistor;
- and
- a switch circuit including at least one MOS transistor for connecting and disconnecting the latch circuit to and from a circuit peripheral to the latch circuit;
- wherein a second source voltage is supplied to the latch circuit independently of a first source voltage that is supplied to the peripheral circuit;
- wherein the switch circuit is turned on and off sequentially with the turning on and off of the first source voltage to the peripheral circuit, and
- wherein the MOS transistors included in the latch circuit and the switch circuit are configured using a low-leakage MOS transistor with a lower leakage current than that of the MOS transistor included in the peripheral circuit.
3 more elements
A semiconductor device comprising:
- a latch circuit including a first and a second data storage node for latching one bit of data electrically in the form of two types of voltages of opposite logic levels and at least one MOS transistor;
- a first switch circuit for connecting and disconnecting the first data storage node to and from a first write bit line;
- a second switch circuit for connecting and disconnecting the second data storage node to and from a second write bit line;
- and
- an output circuit including at least one MOS transistor for outputting a voltage read from the latch circuit onto a read bit line, wherein the input terminal of the output circuit is connected to the first or the second data storage node of the latch circuit via the first or the second switch circuit,
- wherein a second source voltage is supplied to the latch circuit independently of a first source voltage that is supplied to the output circuit,
- wherein the first and the second switch circuits are turned on and off sequentially with the turning on and off of the first source voltage to the output circuit, and
- wherein the MOS transistors included in the latch circuit and the first and second switch circuits are configured using a low-leakage MOS transistor with a lower leakage current than that of the MOS transistor included in the output circuit.
5 more elements
Dependencies are inferred from the claim text.