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US 6,958,947 B2Granted
Semiconductor memory device with internal voltage generators for testing a memory array and peripheral circuits
AssigneeSamsung Electronics Co., Ltd.
InventorsChul-Sung Park, Hyang-Ja Yang, Seung-Min Lee, Yong-Hwan Noh
Life of this patent
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Abstract
A semiconductor memory device which includes an internal voltage generator circuit for adjusting an external power supply voltage and generating first and second internal power supply voltages. The first internal power supply voltage is supplied to a memory cell array via a first power supply line, and the second internal power supply voltage is supplied to a peripheral circuit via a second power supply line. A control circuit controls the internal voltage generator circuit so that the levels of the first and second internal power supply voltages vary depending on a mode of operation.
Claims20
A semiconductor memory device comprising:
- an array memory cells which are arranged in a matrix of rows and columns;
- a data read/write circuit which writes/reads data to/from the array;
- an internal voltage generator circuit which adjusts an external power supply voltage and generates a first internal power supply voltage and a second internal power supply voltage;
- a first power supply line which transfers the first internal power supply voltage to the array;
- a second power supply line which transfers the second internal power supply voltage to the data read/write circuit;
- and
- a control circuit which controls the internal voltage generator circuit so that the first and second internal power supply voltages vary according to an operational mode of the semiconductor memory device:
- wherein at a test mode of operation for controlling a static noise margin of the memory cells, the control circuit controls the internal voltage generator circuit so that the first internal power supply voltage has a lower level than the second internal power supply voltage.
5 more elements
A semiconductor memory device comprising:
- an array of memory cells which are arranged in a matrix of rows and columns;
- a data read/write circuit which writes/reads out data to/from the array;
- an internal voltage generator circuit which adjusts an external power supply voltage and generates a first internal power supply voltage and a second internal power supply voltage;
- a first power supply line which transfers the first internal power supply voltage to the array;
- a second power supply line which transfers the second internal power supply voltage to the data read/write circuit;
- and
- a control circuit which controls the internal voltage generator circuit so that the first and second internal power supply voltage vary according to an operational mode of the semiconductor memory device;
- wherein at a normal mode of operation, the control circuit controls the internal voltage generator circuit so that the first internal power supply voltage has the same level as the second internal power supply voltage, the first and second internal power supply voltages being constantly maintained irrespective of variation of the external power supply voltage.
5 more elements
A semiconductor memory device comprising:
- an array of memory cells which are arranged in a matrix of rows and columns;
- a row selector circuit which selects at least one of the rows in response to a row address;
- a column selector circuit which selects a part of the columns in response to a column address;
- a sense amplifier circuit which senses and amplifies data from memory cells in the selected row and columns;
- a write drive circuit which writes data to the memory cells in the selected row and columns;
- an internal voltage generator circuit which adjusts an external power supply voltage and generates a first internal power supply voltage and a second internal power supply voltage;
- a first power supply line which transfers the first internal power supply voltage to the array;
- a second power supply line which transfers the second internal power supply voltage to the row selector circuit, the column selector circuit, the sense amplifier circuit, and the write driver circuit;
- and
- a control circuit which controls the internal voltage generator circuit so that the second internal power supply voltage has a lower level than the first internal power supply voltage at a package/wafer burn-in test mode of operation;
- wherein at a test mode of operation for controlling a static noise margin of the memory cells, the control circuit controls the internal voltage generator circuit so that the first internal power supply voltage has a lower level than the second internal power supply voltage.
8 more elements
A semiconductor memory device comprising:
- an array of memory cells which are arranged in a matrix of rows and columns;
- a row selector circuit which selects at least one of the rows in response to a row address;
- a column selector circuit which selects a part of the columns in response to a column address;
- a sense amplifier circuit which senses and amplifies data from memory cells in the selected row and columns;
- a write driver circuit which writes data to the memory cells in the selected row and columns;
- an internal voltage generator circuit which adjusts an external power supply voltage and generates a first internal power supply voltage and a second internal power supply voltage;
- a first power supply line which transfers the first internal power supply voltage to the array;
- a second power supply line which transfers the second internal power supply voltage to the row selector circuit, the column selector circuit, the sense amplifier circuit, and the write driver circuit;
- and
- a control circuit which controls the internal voltage generator circuit so that the second internal power supply voltage has a lower level than the first internal power supply voltage at a package/wafer burn-in test mode of operation;
- wherein at a normal mode of operation, the control circuit controls the internal voltage generator circuit so that the first internal power supply voltage has the same level as the second internal power supply voltage, the first and second internal power supply voltages being constantly maintained irrespective of variation of the external power supply voltage.
8 more elements
A semiconductor memory device comprising:
- an array of memory cells which are arranged in a matrix of rows and columns;
- a data read/write circuit which writes/reads out data to/from the array;
- a reference voltage generator circuit which generates a reference voltage of a constant level;
- a first variable reference voltage generator circuit which is supplied with the reference voltage and an external power supply voltage and generates a first variable reference voltage in response to a first control code;
- a second variable reference voltage generator circuit which is supplied with the reference voltage and the external power supply voltage and generates a second variable reference voltage in response to a second control code;
- a first internal voltage generator circuit which is supplied with the external power supply voltage and generates a first internal power supply voltage in response to the first variable reference voltage;
- a first power supply line which transfers the first internal power supply voltage to the array;
- a second internal voltage generator circuit which is supplied with the external power supply voltage and generates a second internal power supply voltage in response to the second variable reference voltage;
- a second power supply line which transfers the second-internal power supply voltage to the data read/write circuit;
- and
- a control circuit which generates the first control code and the second control code in response to a test information,
- wherein at a package/wafer burn-in test mode of operation, the control circuit generates the first and second control codes so that the first internal power supply voltage is established higher than the second internal power supply voltage.
9 more elements
A semiconductor memory device comprising:
- a first generator for supplying a first internal power supply voltage to a memory cell array;
- a second voltage generator for supplying a second internal power supply voltage to one or more peripheral circuits;
- and
- a control circuit for controlling the first and second voltage generators so that the first and second internal power supply voltages vary according to an operational mode of the semiconductor memory device;
- wherein the control circuit controls the first and second voltage generators so that the second internal power supply voltage is greater than the first internal power supply voltage when the semiconductor memory device is in a potential defect property detect mode.
2 more elements
Dependencies are inferred from the claim text.