Flash memory cell having multi-program channels
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChia-Ta Hsieh, Chin-Huang Wang, I-Ming Chang, Hsiang-Tai Lu
Life of this patent
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Abstract
A flash memory cell of an EEPROM split-gate flash memory, the memory cell including a substrate having a plurality of active regions, and a floating gate structure disposed over the substrate. The floating gate structure extends across at least three of the active regions of the substrate such that the floating gate structure and the at least three active regions define at least two channel regions dedicated for programming.
Claims19
A flash memory cell comprising:
- a substrate having a plurality of active regions and a source region;
- and
- a floating gate structure disposed over the substrate, the floating gate structure extending across at least three of the active regions of the substrate and parallel with the source region;
- wherein the floating gate structure and the at least three active regions define at least two channel regions dedicated for programming.
A method of fabricating a flash memory cell, the method comprising the steps of:
- providing a substrate having a plurality of active regions and a source region;
- and
- forming a floating gate structure over the substrate and across at least three of the active regions of the substrate, the floating gate structure parallel with the source region;
- wherein the floating gate structure and the at least three active regions define at least two channel regions dedicated for programming.
A method of programming a flash memory cell having a substrate including a plurality of active regions, a floating gate structure disposed over the substrate and associated with a source region of the substrate, the floating gate structure extending across at least three of the active regions of the substrate, the floating gate structure and the at least three active regions defining at least two channel regions dedicated for programming, and a control gate structure at least partially disposed over the floating gate structure, the control gate structure associated with at least three drain regions of the substrate, the method comprising the steps of:
- applying a programming voltage to a first one of the at least three drain regions;
- and
- applying an inhibiting voltage to a second one of the at least three drain regions.
A method of programming a flash memory cell having a substrate including a plurality of active regions, a floating gate structure disposed over the substrate and associated with a source region of the substrate, the floating gate structure extending across at least three of the active regions of the substrate, the floating gate structure and at least two of the at least three active regions defining two channel regions dedicated for programming, and a control gate structure at least partially disposed over the floating gate structure, the control gate structure associated with at least three drain regions of the substrate, the method comprising the steps of:
- applying a programming voltage to a first one of the at least three drain regions;
- and
- applying an inhibiting voltage to a second one of the at least three drain regions;
- wherein the voltage applying steps are performed simultaneously.
Dependencies are inferred from the claim text.