Data writing method for semiconductor memory device and semiconductor memory device

A data writing method for a semiconductor memory device having a memory cell block capable of rewriting data, said memory cell block having at least two first and second memory cells connected in series or in parallel and adjoined to each other, said method comprising:

• writing data into said first memory cell;
• rewriting the data into said first memory cell when an insufficiency of the data of said first memory cell is determined as a result of verifying the data of said first memory cell at one first reference threshold voltage;
• writing data into said second memory cell following writing the data into said first memory cell;
• and
• rewriting the data into said first memory cell following writing the data into said second memory cell when an insufficiency of the data of said first memory cell is determined as a result of verifying the data of said first memory cell at one second reference threshold voltage, and said first reference threshold voltage is set to be different from said second reference threshold voltage.

A data writing method for a semiconductor memory device having a memory cell block capable of rewriting data, said memory cell block having at least two first and second memory cells connected in series or in parallel and adjoined to each other, and a data control line of said first memory cell and a data control line of said second memory cell adjoin to each other, said method comprising:

• writing data into said first memory cell;
• rewriting the data into said first memory cell when an insufficiency of the data of said first memory cell is determined as a result of verifying the data of said first memory cell at one first reference threshold voltage;
• writing data into said second memory cell following writing the data into said first memory cell;
• and
• rewriting the data into said first memory cell following writing the data into said second memory cell when an insufficiency of the data of said first memory cell is determined as a result of verifying the data of said first memory cell at one second reference threshold voltage, and said first reference threshold voltage is set to be different from said second reference threshold voltage.