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US 6,958,937 B2Granted
DRAM cells with repressed floating gate memory, low tunnel barrier interpoly insulators
AssigneeMicron Technology, Inc.
InventorLeonard Forbes
Life of this patent
Estimating the term…
Abstract
Structures and methods for memory cells having a volatile and a non-volatile component in a single memory cell are provided. The memory cell includes a first source/drain region and a second source/drain region separated by a channel region in a substrate. A floating gate opposes the channel region and separated therefrom by a gate oxide. A control gate opposes the floating gate. The control gate is separated from the floating gate by a low tunnel barrier intergate insulator. The memory cell is adapted to operate in a first and a second mode of operation. The first mode of operation is a dynamic mode of operation and the second mode of operation is a repressed memory mode of operation.
Claims58
A memory comprising:
- a memory cell having a volatile memory component and a non-volatile memory component, the non-volatile memory component including:
- a source region and a drain region separated by a channel region in a substrate;
- a floating gate opposing the channel region;
- a gate oxide separating the floating gate from the channel region, the gate oxide having a first tunneling barrier height;
- a control gate opposing the floating gate;
- and
- a metal oxide insulator separating the control gate from the floating gate, the metal oxide insulator having a second tunneling barrier height, the second tunneling barrier height being less than the first tunneling barrier height;
- and
- a sense amplifier, wherein the memory is adapted to operate the memory cell in a volatile memory mode and a non-volatile memory mode, the memory configured to determine a response time of the sense amplifier to operate the memory cell in the non-volatile memory mode.
6 more elements
A memory comprising:
- a memory cell having a volatile memory component and a non-volatile memory component, the non-volatile memory component including:
- a source region and a drain region separated by a channel region in a substrate;
- a floating gate opposing the channel region;
- a gate oxide separating the floating gate from the channel region, the gate oxide having a first tunneling barrier height;
- a control gate opposing the floating gate;
- and
- a metal oxide insulator separating the control gate from the floating gate, the metal oxide insulator having a second tunneling barrier height of about 2 eV or less than 2 eV, the second tunneling barrier height being less than the first tunneling barrier height;
- and
- a sense amplifier, wherein the memory is adapted to operate the memory cell in a volatile memory mode and a non-volatile memory mode, the memory configured to determine a response time of the sense amplifier to operate the memory cell in the non-volatile memory mode.
6 more elements
A memory comprising:
- a memory cell having a volatile memory component and a non-volatile memory component, the non-volatile memory component including:
- a source region and a drain region separated by a channel region in a substrate;
- a floating gate opposing the channel region;
- a gate oxide separating the floating gate from the channel region, the gate oxide having a first tunneling barrier height;
- a control gate opposing the floating gate;
- and
- an intergate insulator having a plurality of dielectric layers including at least one metal oxide insulator layer, the intergate insulator separating the control gate from the floating gate, the intergate insulator having a second tunneling barrier height and the second tunneling barrier height being less than the first tunneling barrier height;
- and
- a sense amplifier, wherein the memory is adapted to operate the memory cell in a volatile memory mode and a non-volatile memory mode, the memory configured to determine a response time of the sense amplifier to operate the memory cell in the non-volatile memory mode.
6 more elements
A memory comprising:
- a memory cell having a volatile memory component and a non-volatile memory component, the non-volatile memory component including:
- a source region and a drain region separated by a channel region in a substrate;
- a floating gate opposing the channel region;
- a gate oxide separating the floating gate from the channel region, the gate oxide having a first tunneling barrier height;
- a vertical control gate opposing the floating gate;
- an intergate insulator including at least one metal oxide insulator layer, the intergate insulator separating the control gate from the floating gate, the intergate insulator having a second tunneling barrier height and the second tunneling barrier height being less than the first tunneling barrier height;
- and
- a first metal layer separating the intergate insulator and the floating gate, the first metal layer in contact with the floating gate;
- and
- a sense amplifier, wherein the memory is adapted to operate the memory cell in a volatile memory mode and a non-volatile memory mode, the memory configured to determine a response time of the sense amplifier to operate the memory cell in the non-volatile memory mode.
7 more elements
A memory comprising:
- an array of memory cells, each memory cell having a volatile memory component and a non-volatile memory component, the non-volatile memory component including:
- a source region and a drain region separated by a channel region in a substrate;
- a floating gate opposing the channel region;
- a gate oxide separating the floating gate from the channel region, the gate oxide having a first tunneling barrier height;
- a control gate opposing the floating gate;
- and
- an intergate insulator having a metal oxide layer, the intergate insulator separating the control gate from the floating gate, the intergate insulator having a second tunneling barrier height, the second tunneling barrier height being less than the first tunneling barrier height;
- a number of bit lines coupled to the source regions along a first direction in the array of memory cells;
- a number of word lines coupled to the control gates along a second direction in the array of memory cells;
- and
- a number of sense amplifiers coupled to the number of bit lines, wherein the memory is adapted to operate each memory cell in a volatile memory mode and a non-volatile memory mode, the memory configured to determine a response time of each sense amplifier to operate the memory cells in the non-volatile memory mode.
8 more elements
A method of forming a memory, comprising:
- forming a memory cell including:
- forming a source region and a drain region separated by a channel region in a substrate;
- forming a gate oxide on the channel region, the gate oxide having a first tunneling barrier height;
- forming a floating gate opposing the channel region, the floating gate separated from the channel region by the gate oxide;
- forming a control gate opposing the floating gate;
- and
- forming an intergate insulator having a metal oxide insulator layer, the intergate insulator separating the control gate from the floating gate, the intergate insulator having a second tunneling barrier height, the second tunneling barrier height being less than the first tunneling barrier height;
- forming a sense amplifier;
- and
- adapting the memory to operate the memory cell in a volatile memory mode and in a non-volatile memory mode, the memory configured to determine a response time of the sense amplifier to operate the memory cell in the non-volatile memory mode.
7 more elements
A method comprising:
- operating a memory adapted to control a sense amplifier and a memory cell in a volatile memory mode and in a non-volatile memory mode, a memory cell having a volatile memory component and a non-volatile memory component, the memory cell including:
- a source region and a drain region separated by a channel region in a substrate;
- a storage capacitor coupled to one of the source and drain regions;
- a floating gate opposing the channel region;
- a gate oxide separating the floating gate from the channel region, the gate oxide having a first tunneling barrier height;
- a control gate opposing the floating gate;
- and
- an intergate insulator having a metal oxide layer, the intergate insulator separating the control gate from the floating gate, the intergate insulator having a second tunneling barrier height, the second tunneling barrier height being less than the first tunneling barrier height;
- sensing a first charge representing a data value from the storage capacitor if the memory operates the memory cell in the volatile memory mode;
- and
- sensing a second charge representing a data value from the floating gate if the memory operates the memory cell in the non-volatile memory mode, wherein the memory is configured to determine a response time of the sense amplifier to operate the memory cell in the non-volatile memory mode.
8 more elements
Dependencies are inferred from the claim text.