Erase inhibit in non-volatile memories

For a non-volatile memory comprising a plurality of storage elements formed upon a well structure and capacitively coupled thereto, a method comprising:

• selecting one or more but less than all of said storage elements for erase;
• holding the well structure at an erase voltage;
• concurrently with holding the well structure at the erase voltage, raising the voltage level on a control gate of the non-selected storage elements above that which results from the capacitive coupling to the well structure;
• and
• concurrently with holding the well structure at the erase voltage, lowering the voltage level on a control gate of the selected storage elements to below the erase voltage.

A non-volatile memory comprising:

• a plurality of storage units formed upon a substrate;
• a well structure in the substrate upon which the storage units are formed;
• and
• control circuitry connectable to the substrate and a control gate of each of the plurality storage units whereby the voltage level of the well structure and said control gates may be concurrently set to an erase voltage, and further whereby the control gate of selected ones of the storage elements may be allowed to discharge the erase voltage while maintaining the erase voltage on the well structure and non-selected ones of the storage elements.

A system, comprising:

• a memory, comprising:
• a plurality of non-volatile storage units formed upon a substrate and arranged into a plurality of rows and forming one or more columns;
• a well structures in the substrate upon which the storage units are formed;
• a plurality of word lines each connecting a respective control gate of each storage elements of a respective row;
• and
• control circuitry connectable to the substrate and the world lines whereby the voltage level of the well structure and said control gates may be concurrently set to an erase voltage, and further whereby the control gate of selected ones of the storage elements may be allowed to discharge the erase voltage while maintaining the erase voltage on the well structure and non-selected one's of the storage elements;
• a voltage source connectable to the memory wherein the erase voltage is generated;
• and
• a controller connected to the memory for selecting memory cells for erase.

A non-volatile memory comprising:

• a plurality of storage units formed upon a substrate;
• a well structure in the substrate upon which the storage units are formed;
• and
• means for maintaining, during an erase process of selected storage elements, the well structure and non-selected ones of the storage elements at an erase voltage while allowing the control gates of the selected storage elements to discharge.