Nonvolatile semiconductor memory with X8/X16 operation mode using address control
AssigneeSamsung Electronics Co., Ltd.
InventorsHyoung-Woo Lee, June Lee, Oh-Suk Kwon
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Abstract
The present invention relates to a nonvolatile semiconductor memory, that is, a flash memory and especially to a NAND type flash memory device capable of selectively controlling data input/output units by an address control. In the NAND type flash memory device, a memory cell array is divided into a plurality of blocks, and a data input/output path is selectively controlled by a predetermined data rate option and introduced addresses to perform data input/output operations at a ×8 or ×16 speed in one chip.
Claims23
A nonvolatile semiconductor memory device including a plurality of data I/O pins, comprising:
- a memory cell array divided into a plurality of blocks;
- a data rate option selector for generating a data rate control signal according to a predetermined speed option;
- a block selector for generating a plurality of block selection signals to select a block of the memory cell array in response to a predetermined block selection address from column addresses introduced through the I/O pins and the data rate control signal;
- a column selection circuit for selecting a data line in response to a predetermined column selection address from the column addresses, the block selection signals and the data rate control signal and for outputting data of the memory cell array to the selected data line;
- and
- a data I/O controller for selecting a data line to input data to, or output data from, the column selection circuit in response to the block selection signals and the data rate control signal.
A nonvolatile semiconductor memory device comprising:
- a memory cell array divided into 4 blocks;
- a data I/O part including 16 data I/O pins;
- a column address register for sequentially outputting column addresses introduced from the data input/output part according to a synchronization signal;
- a data rate option selector for generating one of an ×8 or ×16 data rate control signal according to a preset data rate option;
- a block selector for generating first through fourth block selection signals to select a block in the memory cell array in response to one or more block selection addresses from the column address register and the data rate control signal;
- a column selection circuit for selecting a data line to input/output data in response to the column selection addresses from the column address register, the first through fourth block selection signals and the data rate control signal, and for outputting the data in the memory to the selected data line;
- a first control circuit for selecting a data line to input/output data in response to the first block selection signal and the second block selection signal;
- and
- a second control circuit for selecting a data line to input/output data in response to the data rate control signal, the third block selection signal and the fourth block selection signal.
Dependencies are inferred from the claim text.