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US 6,958,931 B1Granted
Bit line control and sense amplification for TCCT-based memory cells
AssigneeT-Ram, Inc.
InventorsSei-Seung Yoon, Seong-Ook Jung
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Abstract
A circuit and a method are provided for facilitating control of bit lines in preparation for, or during, sense amplification of data signals from thinly capacitively-coupled thyristor (“TCCT”)-based memory cells. In accordance with a specific embodiment, a circuit and method are designed, among other things, to effectively minimize power consumption by memory cells and to increase speed and reliability of sense amplification. In another specific embodiment, the circuit and method are directed to TCCT-based memory cells.
Claims26
A sensing circuit comprising:
- a sense amplifier;
- a TCCT-based memory cell;
- a reference cell;
- a bit line coupled between the sense amplifier and the TCCT-based memory cell;
- a reference bit line coupled between the sense amplifier and the reference cell;
- and
- a pre-charge device coupled to the bit line and configured to pre-charge the bit line.
4 more elements
A memory array comprising:
- a plurality of TCCT-based memory cells;
- a sense amplifier;
- a bit line coupled to the sense amplifier;
- control circuitry configured to select an individual TCCT-based memory cell from the plurality of TCCT-based memory cells and to couple the individual TCCT-based memory cell to the bit line;
- a reference cell;
- a reference bit line coupled between the sense amplifier and the reference cell;
- and
- a pre-charge device coupled to the bit line and configured to pre-charge the bit line.
5 more elements
Dependencies are inferred from the claim text.