Staggered compare architecture for content addressable memory (CAM) device
AssigneeCypress Semiconductor Corporation
InventorsHari Om, Ajay Srikrishna, Nabil N. Masri
Life of this patent
Estimating the term…
Abstract
A content addressable memory (CAM) device (300) can receive a compare data value having a native word size. The compare data value can be split into smaller portions, with one portion can be applied to a first CAM block (302-0) and another being applied to a second CAM block (302-1) on a subsequent clock (CAMCLK) cycle. Activation of circuit elements in the second CAM block (302-1) can be conditioned on first match results (CMATCHA0 to CMATCHAn) generated by first CAM block (302-0).
Claims21
A method for reducing power consumption in a content addressable memory (CAM) device, comprising the steps of:
- receiving a compare data value of N bits in a CAM device;
- splitting the compare data value into at least two portions within the CAM device;
- and
- temporally staggering a compare operation between the at least two compare data value portions and a plurality of stored data values in the CAM device.
A content addressable memory (CAM) device, comprising:
- a compare data input for receiving a compare data value of N bits at essentially the same time for comparison with a plurality of stored data values;
- a plurality of CAM cell blocks that each store a portion of the stored data values, each portion of the stored data values being less than N bits;
- and
- compare results of a first block of the CAM cell blocks controlling the activation of circuits in at least a second block of the CAM cell blocks.
A content addressable memory (CAM) device, comprising:
- an input for receiving compare data values as N bits in parallel;
- at least a first CAM block including a plurality of first match lines corresponding to first stored data value portions of less than N bits, each first match line providing a first match indication when the corresponding first stored data portion matches a first compare data portion, and providing a second match indication when the corresponding first stored data portion does not match the first compare data portion;
- and
- at least a second CAM block including a plurality of second match lines corresponding to second stored data value portions of less than N bits, each second match line providing a second match indication dependent upon the first match indication of a corresponding first match line.
Dependencies are inferred from the claim text.