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US 6,958,919 B1Granted
Zero voltage switching power conversion circuit for a cold cathode fluorescent lamp
AssigneeSamhop Microelectronics Corp.
InventorYung-Keng Kung
Life of this patent
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Abstract
A zero voltage switching power conversion circuit for driving a CCFL has a ZVS circuit and a full bridge circuit composing of MOS transistors. A transformer is coupled between the full bridge circuit and the CCFL. By properly controlling the conducting timing of each MOS transistor, power is coupled from the primary side to the secondary side of the transformer thus supplying power to the CCFL. When adjusting the brightness of the CCFL, the high frequency signal is able to be temporarily shut down during off periods of the CCFL to reduce power consumption.
Claims20
A zero voltage switching power conversion circuit comprising:
- a zero voltage switching (ZVS) circuit (10) coupled to a full bridge (20) composing of a first pair of transistors (Tr1,Tr2) and a second pair of transistors (Tr3, Tr4), each pair of transistors including a PMOS transistor (Tr1, Tr4) connected to an NMOS transistor (Tr2, Tr3);
- and
- a transformer (30) having a primary side coupled to the full bridge (20) and a secondary side coupled to a load through an output capacitor (C2);
- wherein the ZVS switching circuit (10) further comprises:
- a high frequency oscillation circuit (11), which generates a high frequency signal T1;
- a first divider (12) with an input terminal connected to the high frequency oscillation circuit (11) to receive the high frequency signal T1, wherein the frequency of the high frequency signal T1 is divided by the first divider (12) to obtain a first driving signal P1;
- a first controllable non-overlap circuit (13), which receives the first driving signal P1 from the first divider (12) and generates two non-overlapped signals based on the first driving signal P1;
- a first voltage level booting circuit (14), which boots voltage levels of the two non-overlapped signals output from the first controllable non-overlap circuit (13) so as to derive a first driving signal (Q1) and a second driving signal (Q2) respectively applied to a corresponding one of the first pair of transistors (Tr1, Tr2);
- a voltage-controlled PWM circuit (15) to receive the high frequency signal T1 from the high frequency oscillation circuit (11) and then shifts its phase thus obtaining a phase-shifted high frequency signal T2;
- a second divider (16), which receives the phase-shifted high frequency signal T2, divides the frequency of the phase-shifted high frequency signal T2 to derive a second driving signal P2;
- a second controllable non-overlap circuit (17), which receives the second driving signal P2 from the second divider (16) and generates two non-overlapped signals based on the second driving signal P2;
- and
- a second voltage level booting circuit (18), which boots voltage levels of the two non-overlapped signals output from the second controllable non-overlap circuit (17) to derive a third driving signal (Q3) and a fourth driving signal (Q4) that are respectively applied to a corresponding one of the second pair of transistors (Tr3 Tr4);
- said four driving signals (Q1–Q4) respectively applied to control the four transistors to determine conducting and non-conducting periods of each transistor.
11 more elements
A zero voltage switching power conversion circuit comprising:
- a zero voltage switching (ZVS) circuit (10) coupled to a full bridge (20) composing of a first pair of transistors (Tr1,Tr2) and a second pair of transistors (Tr3, Tr4), each pair of transistors including a PMOS transistor (Tr1, Tr4) connected to an NMOS transistor (Tr2, Tr3);
- and
- a transformer (30) having a primary side coupled to the full bridge (20) and a secondary side coupled to a load through an output capacitor (C2);
- wherein the ZVS switching circuit (10) further comprises:
- a high frequency oscillation circuit (11), which generates a high frequency signal T1;
- a first divider (12) with an input terminal connected to the high frequency oscillation circuit (11) to receive the high frequency signal T1, wherein the frequency of the high frequency signal T1 is divided by the first divider (12) to obtain a first driving signal P1;
- a first controllable non-overlap circuit (13), which receives the first driving signal P1 from the first divider (12) and generates two non-overlapped signals based on the first driving signal P1;
- a first voltage level booting circuit (14), which boots voltage levels of the two non-overlapped signals output from the first controllable non-overlap circuit (13) so as to derive a first driving signal (Q1) and a second driving signal (Q2)*respectively applied to the first pair of transistors (Tr1, Tr2);
- a voltage-controlled delay circuit (19) to receive the high frequency signal T1 from the high frequency oscillation circuit (11) and then delays its phase thus obtaining a phase-shifted high frequency signal T2;
- a second divider (16), which receives the phase-shifted high frequency signal T2, divides the frequency of the phase-shifted high frequency signal T2 to derive a second driving signal P2;
- a second controllable non-overlap circuit (17), which receives the second driving signal P2 from the second divider (16) and generates two non-overlapped signals based on the second driving signal P2;
- and
- a second voltage level booting circuit (18), which boots voltage levels of the two non-overlapped signals output from the second controllable non-overlap circuit (17) to derive a third driving signal (Q3) and a fourth driving signal (Q4) that are *respectively applied to the second pair of transistors (Tr3 Tr4);
- said four driving signals (Q1–Q4) respectively applied to control the four transistors to determine conducting and non-conducting periods of each transistor.
11 more elements
A method for controlling a ZVS power conversion circuit comprising the acts of:
- providing a high frequency signal T1;
- dividing the frequency of said high frequency signal T1 to obtain a first driving signal P1;
- shifting said high frequency signal T1 to obtain a phase-shifted high frequency signal T2;
- dividing the frequency of said phase-shifted high frequency signal T2 to obtain a second driving signal P2, wherein the phase of the second driving signal P2 is different from that of the first driving signal P1;
- generating a first non-overlap signal Q1 and a second non-overlap signal Q2 based on the first driving signal P1;
- generating a third non-overlap signal Q3 and a fourth non-overlap signal Q4 based on the second driving signal P1;
- applying said four non-overlap signals Q1–Q4 to four switching elements of the ZVS power conversion circuit so as to drive a load coupled to the ZVS power conversion circuit.
4 more elements
Dependencies are inferred from the claim text.