Digital-to-analog converter circuits including independently sized reference current source transistors and methods of operating same
AssigneeSamsung Electronics Co., Ltd.
InventorKyeong-tae Moon
Life of this patent
Estimating the term…
Abstract
Digital-to-analog converter circuits can include independently sized first and second current source transistors coupled to respective pluralities of first and second current provider transistors in current mirror configurations. The first and second current provider transistors can be sized proportionally to the first and second current source transistors respectively.
Claims26
An N bit Digital-to-Analog Converter (DAC) comprising independently sized first and second current source transistors coupled to respective pluralities of first and second current provider transistors in current mirror configurations, wherein the first and second current provider transistors are sized proportionally to the first and second current source transistors respectively.
An N bit Digital-to-Analog Converter (DAC) comprising:
- a first current provider circuit configured to provide a plurality of first current signals responsive to a plurality of first bits of an N bit data word weighted differently based on a first reference current;
- and
- a second current provider circuit configured to provide a plurality of second current signals responsive to a plurality of second bits of the N bit data word weighted equally based on a second reference current that is different than the first reference current.
An N bit Digital-to-Analog Converter (DAC) comprising:
- a current correction circuit configured to change at least one of first and second reference currents provided in proportion to respective sizes of transistors included in associated first and second current provider circuits based on a difference between voltage levels provided by the first and second current provider circuits.
A method of operating an N bit Digital-to-Analog Converter (DAC) comprising:
- providing a plurality of first current signals responsive to a plurality of first bits of an N bit data word weighted differently based on a first reference current;
- and
- providing a plurality of second current signals responsive to a plurality of second bits of the N bit data word weighted equally based on a second reference current that is different than the first reference current.
Dependencies are inferred from the claim text.