Test method and apparatus for verifying fabrication of transistors in an integrated circuit

A test apparatus for verifying fabrication of transistors in an integrated circuit, said test apparatus comprising:

• a ring oscillator provided on a die under test during fabrication of said die, said ring oscillator including a plurality of delaying stages connected in cascade, and a like plurality of transfer gates, each transfer gate coupled to a corresponding one of said plurality of delaying stages, each of said transfer gates including a pair of transistors of first and second conductivity types connected in parallel, said transistors of the first conductivity type and said transistors of the second conductivity type being fabricated by the same processes as transistors of the first conductivity type and transistors of the second conductivity type constituting an integrated circuit on said die;
• circuitry operable for measuring
• a first period of said ring oscillator by operating said ring oscillator to provide a first oscillator output signal during a first mode when said transistors of the first conductivity type of each of said transfer gates are ON and said transistors of the second conductivity type of each of said transfer gates are OFF,
• a second period of said ring oscillator by operating said ring oscillator to provide a second oscillator output signal during a second mode when said transistors of the first conductivity type of each of said transfer gates are OFF and said transistors of the second conductivity type of each of said transfer gates are ON, and
• a third period of said ring oscillator by operating said ring oscillator to provide a third oscillator output signal during a third mode when said transistors of the first conductivity type of each of said transfer gates are ON and said transistors of the second conductivity type of each of said transfer gates are ON;
• and
• circuitry operable for analyzing said first, second and third periods for decision making on whether said integrated circuit on said die meets preselected specification.

A computer program product embodied in a storage media, the computer program product including a program of instructions for performing a test method, the test method comprising:

• measuring a first period of a ring oscillator for a die under test,
• wherein said ring oscillator is provided on said die during fabrication of said die, said ring oscillator including a plurality of delaying stages connected in cascade, and a like plurality of transfer gates, each transfer gate coupled to a corresponding one of said plurality of delaying stages, each of said transfer gates including a pair of transistors of first and second conductivity types connected in parallel, said transistors of the first conductivity type and said transistors of the second conductivity type being fabricated by the same processes as transistors of the first conductivity type and transistors of the second conductivity type constituting an integrated circuit on said die,
• said measuring said first period being carried out by operating said ring oscillator to provide a first oscillator output signal during a first mode when said transistors of the first conductivity type of each of said transfer gates are ON and said transistors of the second conductivity type of each of said transfer gates are OFF;
• measuring a second period of said ring oscillator by operating said ring oscillator to provide a second oscillator output signal during a second mode when said transistors of the first conductivity type of each of said transfer gates are OFF and said transistors of the second conductivity type of each of said transfer gates are ON;
• measuring a third period of said ring oscillator by operating said ring oscillator to provide a third oscillator output signal during a third mode when said transistors of the first conductivity type of each of said transfer gates are ON and said transistors of the second conductivity type of each of said transfer gates are ON;
• and
• analyzing said first, second and third periods for decision making on whether said integrated circuit on said die meets preselected specification.