Delay circuit with more-responsively adapting delay time
AssigneeSamsung Electronics Co., Ltd.
InventorYou Mi Lee
Life of this patent
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Abstract
A delay circuit, e.g., for a semiconductor device, having a plurality of cascade-connected stages that successively delay an input signal, may include: plural cascaded-connected delay devices representing instances of a first type of delay unit corresponding to the stages, respectively; plural resistance units coupled between a node having a source voltage of varying magnitude Vvar and odd-numbered ones of the delay devices, respectively; and plural capacitance units coupled between a node having another voltage Vuni of substantially uniform magnitude relative to Vvar and nodes representing the outputs of the odd-numbered delay devices; where corresponding ones of the plurality of capacitor units and the plurality of resistance units represent instances, respectively, of a second type of delay unit.
Claims19
A delay circuit, for a semiconductor device, having a plurality of cascade-connected stages that successively delay an input signal, the delay circuit comprising:
- a plurality of cascaded-connected delay devices representing instances of a first type of delay unit corresponding to the plurality of stages, respectively;
- a plurality of resistance units coupled between a node having a source voltage of varying magnitude Vvar and odd-numbered ones of the plurality of delay devices, respectively;
- and
- a plurality of capacitance units coupled between a node having another voltage Vuni of substantially uniform magnitude relative to Vvar and nodes representing the outputs of the odd-numbered delay devices;
- corresponding ones of the plurality of capacitor units and the plurality of resistance units representing instances, respectively, of a second type of delay unit.
The delay circuit as claimed in 1, wherein each of the plurality of capacitance units is an MOS-type capacitor.
The delay circuit as claimed in 2, wherein each of the plurality of delay devices is an MOS-type inverter.
The delay circuit as claimed in 3, wherein Vvar is externally-supplied.
The delay circuit as claimed in 1, wherein Vuni>Vvar.
The delay circuit as claimed in 1, wherein:
- couplings represented by the plurality of resistance units are indirect types of couplings, respectively:
- and
- even-numbered ones of the plurality of delay devices have direct type couplings, respectively, relative to the indirect couplings.
A delay circuit, for a semiconductor device, having a plurality of cascade-connected stages that successively delay an input signal, the delay circuit comprising:
- a plurality of cascaded-connected delay devices representing instances of a first type of delay unit corresponding to the plurality of stages, respectively;
- a plurality of resistance units coupled between a node having a source voltage of varying magnitude Vvar and odd-numbered ones of the plurality of delay devices, respectively;
- and
- a plurality of capacitance units coupled between a node having a first control voltage V1 of substantially uniform magnitude relative to Vvar and nodes representing the outputs of the odd-numbered delay devices;
- and
- a plurality of switch units controlled by a second control voltage V2 of substantially uniform magnitude relative to Vvar and coupled in parallel with the plurality of resistance units between the node having Vvar and the odd-numbered delay devices, respectively;
- corresponding ones of the plurality of switch units, the plurality of capacitor units and the plurality of resistance units representing instances, respectively, of a second type of delay unit.
The delay circuit as claimed in 7, wherein each of the plurality of capacitance units is an MOS-type capacitor.
The delay circuit as claimed in 7, wherein each of the plurality of delay devices is an MOS-type inverter.
The delay circuit as claimed in 7, wherein Vvar is externally-supplied.
The delay circuit as claimed in 7, wherein V1>Vvar.
The delay circuit as claimed in 7, wherein:
- couplings represented by corresponding ones of the plurality of switching units and the plurality of resistance units are indirect types of couplings, respectively;
- and
- even-numbered ones of the plurality of delay devices have direct type couplings to Vvar, respectively, relative to the indirect couplings.
The delay circuit as claimed in 7, wherein each of the plurality of switch units is an MOS-type transistor.
A delay circuit, for a semiconductor device, having a plurality of cascade-connected stages that successively delay an input signal, the delay circuit comprising:
- a plurality of cascaded-connected delay means, corresponding to the plurality of stages, respectively, for respectively delaying signals passed therethrough;
- a plurality of resistance means for providing impedances to currents flowing between a node having a source voltage of varying magnitude Vvar and odd-numbered ones of the plurality of delay means, respectively;
- and
- a plurality of capacitance means for providing capacitances between a node having another voltage Vuni of substantially uniform magnitude relative to Vvar and nodes representing outputs of the odd-numbered delay means, respectively;
- corresponding ones of the plurality of capacitance means and the plurality of resistance means being operable for providing delays of an RC-type, respectively.
Dependencies are inferred from the claim text.