Low-power direct digital synthesizer with analog interpolation

An integrated circuit comprising:

• a counter operative to receive an input clock signal with a first frequency, an M value and an N value, where the M value and the N value are each integer values, and to generate a counter signal having a second frequency determined by the M value and the N value;
• a delay generator operative to receive the counter signal and an L-bit control signal, where L is an integer greater than one, to generate differential signal based on the counter signal and the L-bit control signal, and to use the differential signal to provide an output clock signal having the second frequency, wherein leading edges of the output clock signal are variably delayed in accordance with the L-bit control signal;
• and
• a current generator operative to provide a reference current for the delay generator, and wherein the variable delay for the leading edges of the output clock signal is obtained based on the reference current.

An integrated

• a counter operative to receive an input clock signal with a first frequency, an M value and an N value, wherein the M value and the N value are each integer value, and to generate a counter signal having a second frequency determined by the M value and the N value;
• a delay generator operative to receive the counter signal and an L-bit control signal, where L is an integer greater than one, to generate a differential signal based on the counter signal and the L-bit control signal, and to use the differential signal to provide an output clock delayed in accordance with the L-bit control, signal;
• and
• a multiplier operative to receive and multiply an accumulator value from the counter with a Q value, where Q is an inverse of the M value and is used to generate the L-bit control signal.

An integrated circuit comprising:

• a counter operative to receive an input clock signal with a first frequency, an M value and an N value, where the M value and the N value are each integer values, and to generate a counter signal having a second frequency determined by the M value and the N value;
• and
• a delay generator operative to receive the counter signal and an L-bit control signal, where L is an integer greater than one, to generate a differential signal based on the counter signal the L-bit control signal, and to use the differential signal to provide an output clock signal having the second frequency, wherein leading edges of the output clock signal are variably delayed in accordance with the L-bit control signal,
• wherein the counter includes:
• a first carry-save adder operative to add the M value with an accumulator value and to provide a first combined value;
• a second carry-save adder operative to subtract the N value from the first combined value and to provide a second combined value and the counter signal, wherein the counter signal includes a pulse whenever an overflow occurs due to the first combined value being greater than or equal to the N value;
• a multiplexer operative, to provide the second combined value if overflow occurs and to provide the first combined value if overflow does not occur;
• and
• a register operative to store die first or second combined value from the multiplexer and to provide the accumulator value.

An integrated circuit comprising:

• a counter operative to receive an input clock signal with a first frequency, an M value and an N value, where the M value and the N value are each integer values, and to generate a counter signal having a second frequency determined by the M value and the N value;
• a delay generator operative to receive the counter signal and an L-bit control signal, where L is an integer greater than one, to generate a differential signal based on the counter signal and the L-bit control signal, and to use the differential signal to provide an output clock signal having the second frequency, wherein leading edges of the output clock signal are variably delayed in accordance with the L-bit control signal;
• and
• a dither generator operative to provide a dither signal, and wherein the counter is further operative to combine the dither signal with the M value and the N value to generate the counter signal.

A device in a communication system,

• a counter operative to receive an input clock signal with a first frequency, an M value, and an N value, where the M value and the N value are integer values, and to generate a counter signal having a second frequency determined by the M value and the N value;
• and
• a delay generator operative to receive the counter signal and an L-bit control signal, where L is an integer value greater than one, to generate a differential signal based on the counter signal and the L-bit control signal, and to use the differential signal to provide an output clock signal having the second frequency, wherein leading edges of the output clock signal are variably delayed in accordance with the L-bit control signal, wherein the delay generator includes:
• a bank of capacitors implemented with thermal decoding, each capacitor in the bank being selectable by the L-bit control signal and having a unit capacitance;
• a current source operative to charge selected capacitors in the bank;
• and
• a comparator operative to provide the output clock signal based on a voltage signal on the selected capacitors in the bank.

A device in a communication system, comprising:

• a counter operative to receive an input clock signal with a first frequency, an M value, and an N value, where the M value and the N value are integer values, and to generate a counter signal having a second frequency determined by the M value and the N value;
• a delay generator operative to receive the counter signal and an L-bit control signal, where L is an integer value greater than one, to generate a differential signal based on the counter signal and the L-bit control signal, and to use the differential signal to provide an output clock signal having the second frequency, wherein leading edges of the output clock signal are variably delayed in accordance with the L-bit control signal;
• and
• a current generator operative to provide a reference current for the delay generator, and wherein the variable delay for the leading edges of the output clock signal is obtained based on the reference current.

A device in a communication system comprising:

• a counter operative to receive an input clock signal with a first frequency, art M value, and an N value, where the M value and the N value are integer values, and to generate a counter signal having a second frequency determined by the M value and the N value;
• a delay generator operative to receive the counter signal and an L-bit control signal, where L is an integer value greater than one, to generate a differential signal based on the counter signal and the L-bit control signal, and to use the differential signal to provide an output clock signal having the second frequency, wherein leading edges of the output clock signal are variably delayed in accordance with the L-bit control signal;
• and
• a multiplier operative to receive and multiply an accumulator value from the counter with a Q value, where the Q value is an inverse of the M value and is used to generate the L-bit control signal.

An apparatus comprising:

• means for receiving an input clock signal with a first frequency, an M value and an N value, where the M value and the N value are each integer valued;
• means for generating a counter signal with the input clock signal and the M value and the N value, wherein the counter signal has a second frequency determined by the M value and the N value;
• means for generating a differential signal based on the counter signal and an L-bit control signal, where L is an integer greater than one;
• means for comparing the differential signal;
• and
• means for providing, based on the comparing, an output clock signal having the second frequency, wherein leading edges of the output clock signal have variable delay determined by the L-bit control signal.