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US 6,958,634 B2Granted
Programmable direct interpolating delay locked loop
AssigneeIntel Corporation
InventorMamun Ur Rashid
Life of this patent
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Abstract
Embodiments of the invention provide for a delay locked loop architecture including a coarse-fine type arrangement using one loop for non-continuous strobe that can be also be configured for continuous clocks as well. In particular, a reference loop establishes precise coarse unit delay. A slave delay line duplicates unit delay. A phase interpolator interpolates between unit delay to produce fine delay.
Claims27
An apparatus, comprising:
- a reference clock;
- a reference feedback circuit that locks to the reference clock and establishes a coarse unit delay;
- a delay circuit that duplicates the coarse unit delay and generates a plurality of coarsely delayed edges, based upon the coarse unit delay;
- and
- a phase interpolator that interpolates between the coarse delay edges to produce a fine delay.
2 more elements
An apparatus
- comprising:
- a delay circuit to generate a plurality of delay strobe edge signals with different phases from a data strobe signal;
- a phase interpolator that generates, from the plurality of delay strobe edge signals, a new delay strobe edge signal having an intermediate phase, wherein the delay circuit to generate a plurality of delay strobe edge signals with different phases from a data strobe signal further comprises:
- a single master loop circuit that includes n master delay elements, locks to a reference clock, and generates a set of bias voltages corresponding to an operating point;
- a slave delay circuit that includes
- n slave delay elements replicated from the master delay elements such that the individual delay is controlled by master loop wherein data strobe passes through the slave delay elements and equally spaced delayed edges are generated;
- multiplexers for selecting adjacent delayed edges from the slave delay elements;
- and
- a phase interpolator to receive the selected adjacent delayed edges and interpolating between the selected adjacent delayed edges to produce a plurality of precision delayed edges.
6 more elements
A method, comprising:
- establishing a coarse unit delay using a reference feedback circuit;
- duplicating the coarse unit delay and generating a plurality of coarsely delayed edges, based upon the coarse unit delay in a delay circuit;
- selecting adjacent coarsely delayed edges;
- and
- interpolating between the selected adjacent coarsely delayed edges to produce a fine delay.
2 more elements
A machine readable medium having stored therein a plurality of machine readable instructions executable by a processor to generate a delay, comprising:
- instructions to establish a coarse unit delay using a reference feedback circuit;
- instructions to duplicate the coarse unit delay and generating a plurality of coarsely delayed edges, based upon the coarse unit delay in a delay circuit;
- and
- instructions to select adjacent coarsely delayed edges;
- and
- instructions to interpolate between the selected adjacent coarsely delayed edges to produce a fine delay.
3 more elements
Dependencies are inferred from the claim text.