Method and related apparatus for non-integer frequency division
AssigneeALi Corporation
InventorHsiuan-Hau Chien
Life of this patent
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Abstract
A method includes generating N reference clocks with period T and phases uniformly distributed in 360 degrees; using each of the N reference clocks to trigger M intermediate signals with period M*T and phases uniformly distributed in 360 degrees; and performing a logic operation between at least two intermediate signals respectively corresponding to two different reference clocks to generate an output clock with period (M/N)*T to achieve non-integer frequency division.
Claims14
A method for performing non-integer frequency division, providing at least an output clock according to a plurality of reference clocks, and making the period of the output clock a predetermined multiple of the period of the reference clocks, the method comprising:
- receiving a plurality of reference clocks, the periods of the reference clocks being the same, and the phases between the different reference clocks being different;
- triggering a plurality of intermediate signals according to each period of the reference clocks, there being M intermediate signals for each reference clock, and making the minimum period of the intermediate signals M times the period of the corresponding reference clock, the phases between the intermediate signals corresponding to the same reference clock being different;
- and
- performing a logic operation between at least two intermediate signals respectively corresponding to two different reference clocks, providing an output clock according to the result of the logic operation, the minimum period of the output clock being shorter than the period of the intermediate signals.
A signal circuit for providing at least one output clock according to a plurality of reference clocks, making the period of the output clock a predetermined multiple of the period of the reference clocks, the signal circuit comprising:
- a reference clock circuit for providing a plurality of reference clocks, the periods of reference clocks being the same, and the phases between the different reference clocks being different;
- a triggering module including a plurality of state machines, each state machine corresponding to a reference clock, for triggering a plurality of corresponding intermediate signals according to each period of the reference clocks, there being M intermediate signals for each reference clock, and for making the minimum period of the intermediate signals M times the period of the corresponding reference clock, the phases between the intermediate signals corresponding to the same reference clock being different;
- and
- a logic module including a plurality of logic gates, the logic module performing a logic operation between at least two intermediate signals respectively corresponding to two different reference clocks, providing an output clock according to the result of the logic operation, the minimum period of the output clock being shorter than the period of the intermediate signals.
Dependencies are inferred from the claim text.