Single stage, level restore circuit with mixed signal inputs
AssigneeIntel Corporation
InventorSapumal Wijeratne
Life of this patent
Estimating the term…
Abstract
A circuit comprises a signal trace to receive a first large signal, a first plurality of signal traces to receive a small signal pair and a clock trace to receive a clock signal. The circuit further comprises a mixed signal circuit having at least a first and a second element, coupled to the signal trace, the first plurality of signal traces and the clock trace. The mixed signal circuit it to facilitate generation of a second large signal based at least in part on the small signal pair and the first large signal, with the first large signal and the clock signal driving the first and second elements respectively to transition asynchronously.
Claims27
A circuit comprising:
- a signal trace to receive a first large signal;
- a first plurality of signal traces to receive a small signal pair;
- a clock trace to receive a clock signal;
- and
- a mixed signal circuit having at least a first and a second element, coupled to the signal trace, the first plurality of signal traces and the clock trace, to facilitate generation of a second large signal based at least in part on the small signal pair and the first large signal, with the first large signal and the clock signal driving the first and second elements respectively to transition asynchronously.
A circuit comprising:
- a first signal trace to receive a first large signal;
- a first plurality of small signal traces to receive a small signal pair;
- a mixed signal circuit coupled to the signal trace and one of the first plurality of small signal traces to facilitate generation of a second large signal on a second signal trace wherein the second large comprises a logic value of a logic function of one small signal of the small signal pair corresponding to the one of the first plurality of signal traces and the first large signal, wherein the first large signal transitions asynchronously to a clock signal.
A system comprising:
- a processor including;
- a circuit comprising:
- a signal trace to receive a first large signal;
- a first plurality of signal traces to receive a small signal pair;
- a clock trace to receive a clock signal;
- and
- a mixed signal circuit having at least a first and a second element, coupled to the signal trace, the first plurality of signal traces and the clock trace, to facilitate generation of a second large signal based at least in part on the small signal pair and the first large signal, with the first large signal and the clock signal driving the first and second elements respectively to transition asynchronously;
- a networking interface;
- a memory configured to store data;
- and
- a bus coupled to the processor, networking interface and memory.
Dependencies are inferred from the claim text.