Three-transistor NAND and NOR gates for two-phase clock generators
AssigneeTexas Instruments Incorporated
InventorAlfio Zanchi
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Abstract
A two-phase non-overlapping clock generator (12) generating a sampling signal (20) utilizing a three transistor NAND gate (50). The NAND gate of the present invention eliminates one large PMOSFET (46), and has one NMOSFET (52) driven by the other phase and having its source grounded. The present invention yields substantial improvement on the jitter of the clock phases. Both rising and falling transitions are improved because of the greatly reduced self-loading of the NAND gate. Overshooting is eliminated, and the NAND gate body effect is minimized, providing enhanced jitter performance of the sampling signal and improving a signal to noise ratio (SNR). The principle of the present invention are also embodied in a NOR gate (70).
Claims47
A circuit, comprising;
- a two-phase non-overlapping signal generator responsive to an external clock and generating a first phase and a second phase, the generator outputting a sampling signal at a sampling rate adapted to control a sampling device, the generator comprising a first NAND gate comprised of two NMOSFETs and only one PMOSFET.
A two-phase non-overlapping clock generator generating a sampling signal, comprising:
- a first NAND gate receiving an external clock and serially coupled to at least a first inverter gate;
- and
- a second NAND gate receiving the external clock and serially coupled to at least a second inverter gate, the first inverter gate being coupled to an input of the second NAND gate, wherein the second NAND gate is comprised of two NMOSFETS and only one PMOSFET.
A two-phase non-overlapped clock generator generating a sample signal, comprising:
- a first NOR gate receiving the external clock and serially coupled to at least a first inverter gate;
- a second NOR gate serially coupled to at least a second inverter gate, said first inverter gate being coupled to an input of the second NOR gate, wherein the second NOR gate is comprised of two PMOSFETS and only one NMOSFET.
A two-phase non-overlapping clock generator generating a sampling signal comprising:
- a first NOR gate receiving an external clock and serially coupled to at least a first inverter gate;
- and
- a second NOR gate receiving the external clock and serially coupled to at least a second inverter gate, the first inverter gate being coupled to an input of the second NOR gate, wherein the second NOR gate is comprised of two PMOSFETS and only one NMOSFET.
Dependencies are inferred from the claim text.