Asynchronous pipeline with latch controllers

An asynchronous digital pipeline circuit for processing data in an environment, the environment providing data for processing and a first request signal, the circuit comprising:

• first processing stage comprising
• first latch controller responsive to a second acknowledgment signal received from a second processing stage and a first done signal received from a first data latch, and configured to assert a first enable signal when the second acknowledgment signal is received and to de-assert the first enable signal when the first done signal is received;
• first data latch configured to receive the data and the first request signal from the environment, wherein each signal transition on the first request signal indicates a new data item, the first data latch having an enabled phase and a disabled phase responsive to the first enable signal, wherein the first data latch is enabled in the enabled phase to pass data from the data input to a data output thereof and the first data latch is disabled in the disabled phase, wherein passing of the data from the first data latch to the data output in the enabled phase also transmits a first acknowledgment signal to the environment, and transmits a first done signal to the first latch controller and a first delay element;
• first logic block configured to receive the data from the first data output, perform a combinational operation on the data, and to transmit the data to the second processing stage;
• and
• first delay element configured to receive the first done signal from the first data latch, apply a delay to the first done signal, and to transmit the delayed first done signal as the second request signal to the second processing stage;
• and
• second processing stage comprising
• second latch controller responsive to a third acknowledgment signal received from the environment and a second done signal received from a second data latch, and configured to assert a second enable signal when the third acknowledgment signal is received and to de-assert the second enable signal when the second done signal is received;
• second data latch configured to receive the data and the second request signal from the first processing stage, wherein each signal transition on the second request signal indicates a new data item, the second data latch having an enabled phase and a disabled phase responsive to the second enable signal, wherein the second data latch is enabled in the enabled phase to pass data from a second data input to a second data output and the second data latch is disabled in the disabled phase, wherein passing of the data from the second data input to the second data output in the enabled phase also transmits the second acknowledgment signal to the first processing stage, and transmits the second done signal to the second latch controller and a second delay element;
• second logic block configured to receive the data from the second data output, perform a combinational operation on the data, and to transmit the data to the environment;
• and
• second delay element configured to receive the second done signal from the second data latch, apply a delay to the second done signal, and to transmit the delayed second done signal as the third request signal to the environment,
• wherein the delay time of the first data latch, tLtN−1, the delay time of the first logic block, tlogicN−1, the rising transition time of the first latch controller, tLCN−11, the falling transition time of the second latch controller, tLCN1, and a hold time, thold, are related by the following equation:
• tLtN−1+tlogicN−1>(tLCN1−tLCN−11)+thold.

An asynchronous digital pipeline circuit for processing data in an environment, the environment providing data for processing and a first and second request signal, the circuit comprising:

• first processing stage comprising
• first latch controller configured to assert a first enable signal when a third acknowledgment signal is received from a third processing stage and to de-assert the first enable signal when a first done signal is received from a first data latch;
• first data latch configured to receive the data and the first request signal from the environment, wherein each signal transition on the first request signal indicates a new data item, the first data latch having an enabled phase and a disabled phase responsive to the first enable signal, wherein the first data latch is enabled in the enabled phase to pass data from a first data input to a first data output and the first data latch is disabled in the disabled phase, wherein passing of the data from the first data input to the first data output in the enabled phase also transmits a first acknowledgment signal to the environment, and transmits a first done signal to the first latch controller and a first delay element;
• first logic block configured to receive the data from the first data output, perform a combinational operation on the data, and to transmit the data to the third processing stage;
• and
• first delay element configured to receive the first done signal from the first data latch, apply a delay to the first done signal, and to transmit the delayed first done signal as a third request signal to the third processing stage;
• second processing stage in parallel with the first processing stage comprising
• second latch controller configured to assert a second enable signal when the third acknowledgment signal is received from the third processing stage and to de-assert the second enable signal when a second done signal is received from a second data latch;
• second data latch configured to receive the data and the second request signal from the environment, wherein each signal transition on the second request signal indicates a new data item, the second data latch having an enabled phase and a disabled phase responsive to the second enable signal, wherein the second data latch is enabled in the enabled phase to pass data from a second data input to a second data output and the second data latch is disabled in the disabled phase, wherein passing of the data from the second data input to the second data output in the enabled phase also transmits a second acknowledgment signal to the environment, and transmits a second done signal to the second latch controller and a second delay element;
• second logic block configured to receive the data from the second data output, perform a combinational operation on the data, and to transmit the data to the third processing stage;
• and
• second delay element configured to receive the second done signal from the second data latch, apply a delay to the second done signal, and to transmit the delayed second done signal as a fourth request signal to the third processing stage;
• and
• third processing stage comprising
• third latch controller comprising configured to assert a third enable signal when a fifth acknowledgment signal is received from the environment and to de-assert the third enable signal when a third done signal is received from a third data latch;
• sequential logic element configured to receive the third enable signal, the third request signal, and the fourth request signal, and to transmit the third done signal;
• third data latch configured to receive the data from the first processing stage and the second processing stage and having an enabled phase and a disabled phase responsive to the third enable signal, wherein the third data latch is enabled in the enabled phase to pass data from a third data input to a third data output and the third data latch is disabled in the disabled phase.