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US 6,958,625 B1Granted
Programmable logic device with hardwired microsequencer
AssigneeLattice Semiconductor Corporation
InventorEdward A. Ramsden
Life of this patent
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Abstract
A programmable logic device configurable to implement a finite state machine includes a hardwired microsequencer for executing microinstructions to sequence the finite state machine. The hardwired microsequencer includes a sequence memory for storing the microinstructions and a program counter.
Claims20
A programmable logic device comprising;
- a programmable logic block including a plurality of macrocells, the macrocells operable to provide logical outputs at the block's output terminals from logical inputs received at the block's input terminals;
- and
- a hardwired microsequencer coupled to the input and output terminals of the programmable logic block, the microsequencer operable to provide a sequence of logical inputs to the programmable logic block, at least part of the sequence determined by logical outputs provided by the macrocells of the programmable logic block.
A method of sequencing a finite state machine, comprising:
- generating input conditions for a finite state machine in a programmable logic block based upon a set of inputs;
- selecting an input condition from the generated input conditions based upon a previously-executed microinstruction selected from a hardwired read-only memory;
- selecting a microinstruction from a set of stored microinstructions in the read-only memory based upon the selected input condition and the previously-executed microinstruction;
- and
- executing the selected microinstruction to provide inputs for the set of inputs.
2 more elements
A programmable logic device, comprising;
- a logic block including a plurality of macrocells, the macrocells operable to provide input conditions for a finite state machine based upon a set of inputs;
- and
- a hardwired microsequencer configured to determine a next state of the finite state machine by cyclically executing a microinstruction selected from a set of microinstructions responsive to cycles of a system clock, wherein at a given cycle of the system clock, the executed microinstruction depends upon the previously-executed microinstruction and an input condition selected from the input conditions provided by the macrocells of the logic block, and wherein the set of inputs for the logic block includes inputs derived from the executed microinstruction.
Dependencies are inferred from the claim text.