Data latch with low-power bypass mode
AssigneeAltera Corporation
InventorsGregory Starr, Martin Langhammer, Chiao Kai Hwang
Life of this patent
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Abstract
A bypassable latch circuit consumes less power in the bypass mode than it does in the latched mode. The circuit includes a flip-flop whose output is routed to an input of a multiplexer. The other input of the multiplexer is the input of the flip-flop as well. The multiplexer is used to select as the latch output either the registered or latched flip-flop output, or the flip-flop input. The flip-flop is modified by replacing the inverter at the flip-flop clock input with a logic gate that accepts as inputs both the clock input and a control input. The control input can cause the flip-flop to ignore the clock, preventing switching that consumes power by charging and discharging capacitive elements in the flip-flop.
Claims22
A logic circuit comprising:
- functional circuitry including a data input and a data output;
- a selector element for bypassing said functional circuitry, said selector element having a logic output and a selector input, said logic output being selectable between said data input and said data output under control of a signal on said selector input;
- wherein:
- said functional circuitry switches, responsive to said signal, between (a) operation in a normal mode, and (b) operation in a low-power mode.
Dependencies are inferred from the claim text.