Method for dual-layer polyimide processing on bumping technology

A conductive bump formed on a semiconductor surface, overlying a layer of Under Bump Metallization (UBM) comprising:

• a semiconductor surface, said semiconductor surface having been provided with integrated circuitry,
• at least one layer of passivation over said semiconductor surface, said at least one layer of passivation comprising PE Si3N4 having a thickness between about 200 and 800 Angstrom, at least one contact pad in or over said substrate;
• access to said integrated circuitry for external contact by at least one first via having a first diameter extending through said at least one layer of passivation, said at least one first via being aligned with said at least one contact pad;
• at least one layer of negative photoresist over said at least one layer of passivation, further at least one layer of polyimide insulator over said at least one layer of negative photoresist, said layer of at least one layer of polyimide insulator having a thickness between about 300 and 800 Angstrom;
• access to said integrated circuitry for external contact by at least one second via having a second diameter through said at least one layer of polyimide insulator, further through said at least one layer of negative photoresist, said second diameter being smaller than said first diameter, said second via being aligned with said first via;
• a layer of UBM metal over said at least one layer of polyimide insulator, with a portion of said layer of UBM metal extending into said at least one second via and further extending into said at least one first via to make electrical contact with said integrated circuitry, said layer of UBM metal comprising one or more layers of different metallic composition;
• and
• a layer of solder or a compound thereof over said layer of UBM metal, said layer of solder or a compound thereof being aligned with said at least one second via.