Semiconductor equipment with lateral and vertical MOS regions

Semiconductor equipment comprising:

• a plurality of first type semiconductor devices having first and second device regions;
• a plurality of second type semiconductor devices having the first and second device regions;
• and
• upper and lower layer wirings,
• wherein the upper and lower layer wirings connect the first and second device regions together with a parallel connection,
• wherein the lower layer wiring includes a first contact for connecting to the first device region, the first contact being concentrated into a predetermined area of the semiconductor equipment,
• wherein the lower layer wiring further includes a second contact for connecting to the second device region, the second contact surrounding the first contact, and
• wherein the upper layer wiring disposed on the predetermined area provides a pad area for connecting to an external circuit.

Semiconductor equipment comprising:

• a semiconductor substrate;
• a plurality of first type semiconductor devices having first and second device regions, the devices disposed on the substrate;
• a plurality of second type semiconductor devices having the first and second device regions, the devices disposed on the substrate;
• and
• upper and lower layer wirings disposed on the substrate,
• wherein the upper and lower layer wirings electrically connect a plurality of first device regions together with a parallel connection, and connect a plurality of second device regions together with a parallel connection,
• wherein the lower layer wiring includes a first contact for connecting to the first device region of at least one of the first or second type semiconductor device, the first contact being concentrated into a predetermined area of the semiconductor equipment,
• wherein the lower layer wiring further includes a second contact for connecting to the second device region, the second contact surrounding the first contact,
• wherein the upper layer wiring disposed on the predetermined area provides a pad area for connecting to an external circuit,
• wherein the semiconductor substrate includes a first semiconductor layer having a first conductive type and a second semiconductor layer having a first conductive type,
• wherein the second semiconductor layer is disposed on the first semiconductor layer, and has a doping concentration lower than that of the first semiconductor layer,
• wherein the first type semiconductor device is a lateral type metal oxide semiconductor transistor, which includes a second conductive type channel diffusion region disposed on a surface portion of the second semiconductor layer, a first conductive type source diffusion region disposed on a surface portion of the channel diffusion region, a gate electrode contacting a part of the channel diffusion region through a gate insulation film, and a first conductive type drain diffusion region disposed on a surface portion of the second semiconductor layer so as to separate from the source diffusion region,
• wherein the second type semiconductor device is a vertical type metal oxide semiconductor transistor, which includes a second conductive type channel diffusion region disposed on a surface portion of the second semiconductor layer, a first conductive type source diffusion region disposed on a surface portion of the channel diffusion region, a gate electrode contacting a part of the channel diffusion region through a gate insulation film, and a first conductive type drain connection diffusion region,
• wherein the drain connection diffusion region separates from the source diffusion region, is disposed from the surface of the second semiconductor layer, and reaches the first semiconductor layer,
• wherein the first device region is a source of the lateral type metal oxide semiconductor transistor and the vertical type metal oxide semiconductor transistor,
• wherein the second device region is a drain of the lateral type metal oxide semiconductor transistor and the vertical type metal oxide semiconductor transistor, and
• wherein the first contact connects to the source of the vertical type metal oxide semiconductor transistor.

Semiconductor equipment comprising:

• a semiconductor substrate;
• a plurality of first type semiconductor devices having first and second device regions, the devices disposed on the substrate;
• a plurality of second type semiconductor devices having the first and second device regions, the devices disposed on the substrate;
• and
• upper and lower layer wirings disposed on the substrate,
• wherein the upper and lower layer wirings electrically connect a plurality of first device regions together with a parallel connection, and connect a plurality of second device regions together with a parallel connection,
• wherein the lower layer wiring includes a first contact for connecting to the first device region of at least one of the first or second type semiconductor device, the first contact being concentrated into a predetermined area of the semiconductor equipment,
• wherein the lower layer wiring further includes a second contact for connecting to the second device region, the second contact surrounding the first contact,
• wherein the upper layer wiring disposed on the predetermined area provides a pad area for connecting to an external circuit
• wherein the semiconductor substrate includes a semiconductor layer having a first conductive type,
• wherein the first and second type semiconductor devices are lateral type metal oxide semiconductor transistors, which includes a second conductive type channel diffusion region disposed on a surface portion of the second semiconductor layer, a first conductive type source diffusion region disposed on a surface portion of the channel diffusion region, a gate electrode contacting a part of the channel diffusion region through a gate insulation film, and a first conductive type drain diffusion region disposed on a surface portion of the semiconductor layer so as to separate from the source diffusion region,
• wherein the first and second device regions in the first type semiconductor device are aligned alternately on the semiconductor substrate, and have an almost square shape in a plan view,
• wherein the first and second device regions in the second type semiconductor device are aligned alternately on the semiconductor substrate, and have an almost rectangular shape in a plan view,
• wherein the first device region is a source of the first and second type semiconductor devices,
• wherein the second device region is a drain of the first and second type semiconductor devices, and
• wherein the first contact concentrated into the predetermined area of the semiconductor equipment connects to the source of the second type semiconductor device.

Semiconductor equipment comprising:

• a semiconductor substrate;
• a plurality of first type semiconductor devices having first and second device regions, the devices disposed on the substrate;
• a plurality of second type semiconductor devices having the first and second device regions, the devices disposed on the substrate;
• and
• upper and lower layer wirings disposed on the substrate,
• wherein the upper and lower layer wirings electrically connect a plurality of first device regions together with a parallel connection, and connect a plurality of second device regions together with a parallel connection,
• wherein the lower layer wiring includes a first contact for connecting to the first device region of at least one of the first or second type semiconductor device, the first contact being concentrated into a predetermined area of the semiconductor equipment,
• wherein the lower layer wiring further includes a second contact for connecting to the second device region, the second contact surrounding the first contact,
• wherein the upper layer wiring disposed on the predetermined area provides a pad area for connecting to an external circuit,
• wherein the semiconductor substrate includes a semiconductor layer having a first conductive type,
• wherein the first and second type semiconductor devices are lateral type metal oxide semiconductor transistors, which includes a second conductive type channel diffusion region disposed on a surface portion of the second semiconductor layer, a first conductive type source diffusion region disposed on a surface portion of the channel diffusion region, a gate electrode contacting a part of the channel diffusion region through a gate insulation film, and a first conductive type drain diffusion region disposed on a surface portion of the semiconductor layer so as to separate from the source diffusion region,
• wherein the first and second device regions in the first type semiconductor device are aligned alternately on the semiconductor substrate, and have an almost square shape in a plan view,
• wherein the first and second device regions in the second type semiconductor device are aligned alternately on the semiconductor substrate, and have an almost rectangular shape in a plan view,
• wherein the first device region is a drain of the first and second type semiconductor devices,
• wherein the second device region is a source of the first and second type semiconductor devices, and
• wherein the first contact connects to the first device region of the second type semiconductor device, and concentrates into the predetermined area of the second type semiconductor device.

Semiconductor equipment comprising:

• a plurality of first type semiconductor devices having first and second device regions;
• a plurality of second type semiconductor devices having the first and second device regions;
• upper and lower layer wirings;
• and
• a semiconductor substrate including a first semiconductor layer with a first conductive type and a second semiconductor layer with a first conductive type,
• wherein the upper and lower layer wirings connect the first and second device regions together with a parallel connection,
• wherein the lower layer wiring includes a first contact for connecting to the first device region, the first contact being concentrated into a predetermined area of the semiconductor equipment,
• wherein the lower layer wiring further includes a second contact for connecting to the second device region, the second contact surrounding the first contact,
• wherein the upper layer wiring disposed on the predetermined area provides a pad area for connecting to an external circuit
• wherein the second semiconductor layer is disposed on the first semiconductor layer,
• wherein the first type semiconductor device is a lateral diffused metal oxide semiconductor transistor, which includes a second conductive type channel diffusion region disposed on a surface portion of the second semiconductor layer, a first conductive type source diffusion region disposed on a surface portion of the channel diffusion region, a gate electrode contacting a part of the channel diffusion region through a gate insulation film, and a first conductive type drain diffusion region disposed on a surface portion of the second semiconductor layer so as to separate from the source diffusion region,
• wherein the second type semiconductor device is a vertically diffused metal oxide semiconductor transistor, which includes a second conductive type channel diffusion region disposed on a surface portion of the second semiconductor layer, a first conductive type source diffusion region disposed on a surface portion of the channel diffusion region, a gate electrode contacting a part of the channel diffusion region through a gate insulation film, and a first conductive type drain connection diffusion region,
• wherein the drain connection diffusion region separates from the source diffusion region, is disposed from the surface of the second semiconductor layer, and reaches the first semiconductor layer,
• wherein the first device region is a source of the laterally diffused metal oxide semiconductor transistor and the vertically diffused metal oxide semiconductor transistor,
• wherein the second device region is a drain of the laterally diffused metal oxide semiconductor transistor and the vertically diffused metal oxide semiconductor transistor, and
• wherein the first contact connects to the source of the vertically diffused metal oxide semiconductor transistor.