Multiple chip semiconductor package

A semiconductor device package comprising:

• a substrate;
• a first dielectric layer disposed over a surface of the substrate;
• a first conductive trace layer disposed over the first dielectric layer;
• at least one additional dielectric layer disposed over the first conductive trace layer;
• at least one additional conductive trace layer disposed over the at least one additional dielectric layer, the at least one additional dielectric layer being electrically coupled with the first conductive trace layer;
• a final dielectric layer disposed over the at least one additional conductive trace layer;
• a plurality of semiconductor dice, each semiconductor die of the plurality of semiconductor dice having a plurality of signal connection devices, wherein:
• the plurality of signal connection devices is electrically coupled with the at least one additional conductive trace layer;
• an encapsulation layer disposed over the plurality of semiconductor dice;
• and
• a plurality of circuit connection elements electrically coupled with the first conductive trace layer, wherein each of the plurality of circuit connection elements extends through the first dielectric layer and the at least one additional dielectric layer, and has a portion thereof exposed through the encapsulation layer.

A memory device comprising:

• a carrier substrate;
• a plurality of electrical contacts coupled with electrical circuitry formed in the carrier substrate;
• and
• at least one semiconductor device package coupled with the electrical circuitry in the carrier substrate, the at least one semiconductor device package comprising:
• a substrate;
• a first dielectric layer disposed over a surface of the substrate;
• a conductive trace layer disposed over the first dielectric layer;
• a second dielectric layer disposed over the conductive trace layer, the second dielectric layer defining a plurality of vias therethrough exposing a plurality of connection areas on the conductive trace layer;
• a metallization layer electrically coupled with the plurality of connection areas;
• a plurality of semiconductor dice, each semiconductor die of the plurality of semiconductor dice having a plurality of signal connection devices wherein the plurality of signal connection devices is electrically coupled with the metallization layer;
• an encapsulation layer disposed over the plurality of semiconductor dice;
• and
• a plurality of circuit connection elements electrically coupled to the conductive trace layer, wherein each of the plurality of circuit connection elements extends through the first dielectric layer and the second dielectric layer, and has a portion thereof exposed through the encapsulation layer.

A computing system comprising:

• a carrier substrate;
• a processor operably coupled to circuitry formed in the carrier substrate;
• at least one input device operably coupled with the circuitry formed in the carrier substrate;
• at least one output device operably coupled with the circuitry formed in the carrier substrate;
• and
• a memory device operably coupled to the circuitry formed in the carrier substrate, the memory device including at least one semiconductor device package, the at least one semiconductor device package comprising:
• a substrate;
• a first dielectric layer disposed over a surface of the substrate;
• a conductive trace layer disposed over the first dielectric layer;
• a second dielectric layer disposed over the conductive trace layer, the second dielectric layer defining a plurality of vias therethrough exposing a plurality of connection areas on the conductive trace layer;
• a metallization layer electrically coupled with the plurality of connection areas;
• a plurality of semiconductor dice, each semiconductor die of the plurality of semiconductor dice having a plurality of signal connection devices wherein the plurality of signal connection devices is electrically coupled with the metallization layer;
• an encapsulation layer disposed over the plurality of semiconductor dice;
• and
• a plurality of circuit connection elements electrically coupled to the conductive trace layer, wherein each of the plurality of circuit connection elements extends through the first dielectric layer and the second dielectric layer, and has a portion thereof exposed through the encapsulation layer.

A computing system comprising:

• a carrier substrate;
• at least one input device operably coupled with circuitry formed in the carrier substrate;
• at least one output device operably coupled with the circuitry formed in the carrier substrate;
• and
• at least one semiconductor device package operably coupled with the circuitry formed in the carrier substrate, the at least one semiconductor device package comprising:
• a substrate;
• a first dielectric layer disposed over a surface of the substrate;
• a conductive trace layer disposed over the first dielectric layer;
• a second dielectric layer disposed over the conductive trace layer, the second dielectric layer defining a plurality of vias therethrough exposing a plurality of connection areas on the conductive trace layer;
• a metallization layer electrically coupled with the plurality of connection areas;
• a plurality of semiconductor dice, each semiconductor die of the plurality of semiconductor dice having a plurality of signal connection devices wherein the plurality of signal connection devices is electrically coupled with the metallization layer;
• an encapsulation layer disposed over the plurality of semiconductor dice;
• and
• a plurality of circuit connection elements electrically coupled to the conductive trace layer, wherein each of the plurality of circuit connection elements extends through the first dielectric layer and the second dielectric layer, and has a portion thereof exposed through the encapsulation layer.