Insulating layer having graded densification

A method of manufacturing an integrated circuit device, comprising:

• forming a first dielectric layer having a first pore size over a substrate having a plurality of micro-electronic devices located therein;
• shrinking the first pore size to a second pore size by a first densification process;
• forming a second dielectric layer over the first dielectric layer;
• increasing an aggregate dielectric constant of the first and second dielectric layers by a second densification process;
• and
• forming a plurality of interconnects in the first and second dielectric layers to interconnect ones of the plurality of micro-electronic devices.

An integrated circuit device, comprising:

• a substrate having a plurality of micro-electronic devices located therein;
• a first dielectric layer having a first pore size located over the substrate;
• a second dielectric layer having a second pore size located over the first dielectric layer, wherein the second pore size is larger than the first pore size;
• and
• interconnects located in the first and second dielectric layers and interconnecting ones of the plurality of micro-electronic devices.

A method of manufacturing an integrated circuit device, comprising:

• forming a plurality of overlying dielectric layers over a substrate, the substrate including a plurality of micro-electronic devices located therein;
• shrinking a first pore size of at least one of the plurality of overlying dielectric layers to a second pore size by a densification process prior to forming other overlying ones of the plurality of overlying dielectric layers;
• increasing an aggregate dielectric constant of at least one of the plurality of overlying dielectric layers by a second densification process;
• and
• forming a plurality of interconnects in ones of the plurality of overlying dielectric layers to interconnect ones of the micro-electronic devices.