Semiconductor device having at least one source/drain region formed on an isolation region and a method of manufacture therefor

A semiconductor device, comprising:

• a channel region located in a semiconductor substrate;
• a trench located adjacent a side of the channel region;
• an isolation region formed over the semiconductor substrate, the isolation region having a first portion within a trench formed in the semiconductor substrate and a second post portion extending above the first portion, wherein the second post portion is narrower in width than the first portion and extends above the semiconductor substrate, and wherein no structural interface exists between the first and second portions of the isolation region;
• and
• a first portion of one of source/drain region formed in the semiconductor substrate and a second portion of the one of the source/drain region formed on the isolation region and in contact with the second post portion but not in the semiconductor substrate wherein the second portion of the one of the source/drain region comprises polysilicon.

A semiconductor device, comprising:

• a channel region located in a semiconductor substrate;
• an isolation region located adjacent but not extending under the channel region the isolation region having a first portion within a trench formed in the semiconductor substrate and a second post portion extending above the first portion, wherein the second post portion is narrower in width than the first portion and extends above the semiconductor substrate, and, wherein no structural interface exists between the first and second portions of the isolation region;
• and
• source/drain regions having a first portion located in the semiconductor substrate and a second portion located on the isolation region and in contact with the second post portion, but not in the semiconductor substrate wherein the second portion of the one of the source/drain region comprises polysilicon.

A semiconductor device, comprising:

• a first transistor located adjacent a second transistor, wherein both the first and second transistors are located over a semiconductor substrate;
• an isolation region located between the first and second transistors, the isolation region having a first portion within a trench formed in the semiconductor substrate and a second post portion extending above the first portion, wherein the second post portion is narrower in width than the first portion and extends above the semiconductor substrate, and wherein no structural interface exists between the first and second portions of the isolation region;
• and
• source/drain regions associated with each of the first and second transistors, each of the source/drain regions having a first portion located in the semiconductor substrate and a second portion located on the isolation region and in contact with the second post portion, but not in the semiconductor substrate wherein the second portion of the one of the source/drain region comprises polysilicon.

A method of manufacturing a semiconductor device, comprising:

• providing a semiconductor substrate;
• creating a gate above the semiconductor substrate, the gate having gate sidewall spacers located along sidewalls thereof;
• forming an isolation region having a first portion within a trench formed in the semiconductor substrate and a second post portion extending above the first portion, wherein the second post portion is narrower in width than the first portion and extends above the semiconductor substrate, and, wherein no structural interface exists between the first and second portions of the isolation region;
• forming a first portion of one of a source/drain region in the semiconductor substrate and a second portion of the one of the source/drain region on the isolation region and in contact with the second post portion but not in the semiconductor substrate wherein the second portion of the one of the source/drain region comprises polysilicon.

An integrated circuit, comprising:

• semiconductor devices, including;
• a semiconductor substrate;
• a gate formed above the semiconductor substrate, the gate having gate sidewall spacers located along sidewalls thereof;
• an isolation region having a first portion within a trench formed in the semiconductor substrate and a second post portion extending above the first portion, wherein the second post portion is narrower in width than the first portion and extends above the semiconductor substrate, and wherein no structural interface exists between the first and second portions of the isolation region;
• a first of one of a source/drain region formed in the semiconductor substrate and a second portion of the one of the source/drain region formed on the isolation region and in contact with the second post portion but not in the semiconductor substrate wherein the second portion of the one of the source/drain region comprises polysilicon;
• and
• interconnect structures contacting the semiconductor devices.