US 6,958,513 B2 · Floating-gate memory cell having trench structure with ballistic-charge injector, and the array of memory cells

Abstract

A method of forming an array of floating gate memory cells, and an array formed thereby, wherein each memory cell includes an electrical conductive floating gate formed in a trench in a semiconductor substrate, and an electrical conductive control gate having a portion disposed over and insulated from the floating gate. An electrical conductive tunneling gate is disposed over and insulated from the control gate by an insulating layer to form a tri-layer structure permitting both electron and hole charges tunneling through at similar tunneling rate. Spaced apart source and drain regions are formed with the source region disposed adjacent to and insulated from a lower portion of the floating gate, and with the drain region disposed adjacent to and insulated from an upper portion of the floating gate with a channel region formed therebetween and along a sidewall of the trench.

Claims64

Dependent claims

An electrically erasable and programmable read only memory device comprising:

a bulk material;
a first layer of semiconductor material over said bulk material and having a first conductivity type;
a first region formed in between said bulk material and said first layer, and having a second conductivity type;
a trench formed into a surface of said first layer and having a sidewall and a bottom;
a second region formed in said first layer, laterally adjacent to an upper portion of said trench, and having the second conductivity type;
a channel region in said first between said first region and said second region, and extending generally along said sidewall of said trench;
an electrically conductive floating gate disposed adjacent to and insulated from said channel region;
an electrically conductive control gate having at least a portion thereof disposed over and insulated from said floating gate;
and
an electrically conductive tunneling gate disposed over and insulated from at least a portion of said control gate.

7 more elements

An array of electrically programmable and erasable memory devices comprising:

a bulk material;
a first layer of semiconductor material over said bulk material and having a first conductivity type;
spaced apart isolation regions formed in said first layer which are generally parallel to one another and extend in a first direction, with an active region between each pair of adjacent isolation regions;
spaced apart drain-lines extend in said first direction with each of said drain-line formed in at least a portion of said active region and next to the surface of said first layer;
each of said active regions including a plurality of memory cells, each of the memory cells comprising:
a first region formed in between said bulk material and said first layer, and having a second conductivity type;
a trench formed into a surface of said first layer and having a sidewall and a bottom;
a second region formed in said first layer, laterally adjacent to an upper portion of said trench, and having the second conductivity type;
a channel region in said first layer between said first region and said second region, and extending generally along said sidewall of said trench;
an electrically conductive floating gate disposed adjacent to and insulated from said channel region;
an electrically conductive control gate having at least a portion thereof disposed over and insulated from said floating gate;
and
an electrically conductive tunneling gate disposed over and insulated from at least a portion of said control gate.

10 more elements

Dependencies are inferred from the claim text.

Floating-gate memory cell having trench structure with ballistic-charge injector, and the array of memory cells

Life of this patent

Floating-gate memory cell having trench structure with ballistic-charge injector, and the array of memory cells

Life of this patent

Abstract

Claims64