Flash memory device and method of fabrication thereof including a bottom oxide layer with two regions with different concentrations of nitrogen

A process of fabricating a multi-bit charge trapping dielectric flash memory device, comprising:

• providing a semiconductor substrate;
• forming on the semiconductor substrate a bottom oxide layer having a first side and a second side including a substrate/oxide interface adjacent the semiconductor substrate, wherein the bottom oxide layer comprises a material having a general formula SixOyNz1, wherein x, y and z1 are atomic percentages;
• and
• adding a quantity of nitrogen to the bottom oxide layer, whereby the bottom oxide layer comprises a fist region adjacent the first side and a second region adjacent the substrate/oxide interface, whereby z1 does not substantially change in the first region and the second region comprises a material having a general formula SixOyNz2, wherein x, y and z2 are atomic percentages, and y>z2>z1.

A charge trapping dielectric flash memory device, comprising:

• a semiconductor substrate having an upper surface;
• a bottom oxide layer having a lower surface, the bottom oxide layer formed on the upper surface of the substrate, whereby a substrate/oxide interface is defined by the upper surface and the lower surface;
• and
• a charge trapping dielectric charge storage layer over the bottom oxide layer,
• wherein the bottom oxide layer comprises a first region adjacent the charge storage layer and a second region adjacent the substrate/oxide interface, the first region comprising a material having a general formula SixOyNz1, the second region comprising a material having a general formula SixOyNz2, wherein x, y, z1 and z2 are atomic percentages, and y>z2>z1 wherein z1 is in a range from zero to about 20 percent.