Process for fabricating a dual charge storage location memory cell

A dual charge storage, electrically programmable memory cell, comprising:

• a semiconductor layer of a first conductivity type;
• first and second doped regions spaced apart from each other in the semiconductor layer, the doped regions being of a second conductivity type;
• first and second charge storage regions spaced apart from each other above the semiconductor layer and positioned adjacent to the first and second doped regions, respectively, wherein the charge storage regions are physically separated and composed of silicon nitride;
• a central dielectric layer positioned between, without extending on, the first and second charge storage regions;
• a conductive control gate positioned over the central dielectric layer and the first and second charge storage regions, and being insulated from the first and second charge storage regions;
• a first gate dielectric layer underlying the charge storage regions and the central dielectric layer and positioned on the channel region;
• and
• a second gate dielectric layer positioned on the central dielectric layer and between the charge storage regions and the conductive control gate.