Magnetic random access memory cell
AssigneeInternational Business Machines Corporation
InventorYu Lu
Life of this patent
Estimating the term…
Abstract
A memory cell for use in a magnetic random access memory (MRAM) circuit includes at least first and second transistors formed in a semiconductor layer. A first insulating layer is formed on at least a portion of the first and second transistors. The memory cell further includes a first magnetic storage element formed on at least a portion of the first insulating layer, at least a second insulating layer formed on at least a portion of the first magnetic storage element, and at least a second magnetic storage element formed on at least a portion of the second insulating layer. The first and second magnetic storage elements are electrically connected to the first and second transistors, respectively.
Claims23
A memory cell for use in a magnetic random access memory (MRAM) circuit, the memory cell comprising:
- a first transistor formed in a semiconductor layer, the first transistor comprising first and second source/drain regions and a gate;
- at least a second transistor formed in the semiconductor layer, the second transistor comprising first and second source/drain regions and a gate;
- a first insulating layer formed on at least a portion of the first and second transistors;
- a first magnetic storage element formed on the first insulating layer, the first magnetic storage element being electrically connected to the first transistor;
- at least a second insulating layer formed on at least a portion of the first magnetic storage element;
- and
- at least a second magnetic storage element formed on the second insulating layer, the second magnetic storage element being electrically connected to the second transistor.
A magnetic random access memory (MRAM) array, comprising:
- a plurality of memory cells, at least one of the memory cells comprising:
- a first transistor formed in a semiconductor layer, the first transistor comprising first and second source/drain regions and a gate;
- at least a second transistor formed in the semiconductor layer, the second transistor comprising first and second source/drain regions and a gate;
- a first insulating layer formed on at least a portion of the first and second transistors;
- a first magnetic storage element formed on at least a portion of the first insulating layer, the first magnetic storage element being electrically connected to the first transistor;
- at least a second insulating layer formed on at least a portion of the first magnetic storage element;
- and
- at least a second magnetic storage element formed on at least a portion of the second insulating layer, the second magnetic storage element being electrically connected to the second transistor;
- and
- a plurality of bit lines and word lines operatively coupled to the memory cells for selectively reading and writing one or more memory cells in the MRAM array.
An integrated circuit device including at least one memory cell, the at least one memory cell comprising:
- first and second transistors formed in a semiconductor layer;
- a first insulating layer formed on at least a portion of the first and second transistors;
- a first magnetic storage element formed on at least a portion of the first insulating layer, the first magnetic storage element being electrically connected to the first transistor;
- at least a second insulating layer formed on at least a portion of the first magnetic storage element;
- and
- at least a second magnetic storage element formed on at least a portion of the second insulating layer, the second magnetic storage element being electrically connected to the second transistor.
Dependencies are inferred from the claim text.