Semiconductor device and manufacturing method thereof
AssigneeTrecenti Technologies, Inc.
InventorKenji Tokunaga
Life of this patent
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Abstract
In a semiconductor device manufacturing process using a low-dielectric-constant insulation film as an interlayer insulation film, a stress exerted on wiring layers and interlayer insulation films is reduced. In a semiconductor device in which a plurality of buried wiring layers are formed in the interlayer insulation films each formed of a low-dielectric-constant insulation film lower in mechanical strength than a silicone oxide film formed by, for example, a CVD method, a first layer of wiring, on a lower layer of which a low-dielectric-constant insulation film is not disposed, serves as a bonding pad, and bump electrodes are formed on the wiring so as to become higher than a position where the uppermost buried wiring is formed.
Claims7
A manufacturing method of a semiconductor device, the method comprising the steps of:
- (a) forming a first insulation film over a semiconductor substrate;
- (b) forming a first wiring layer over said first insulation film;
- (c) forming, over said first wiring layer, a second insulation film lower in dielectric constant than said first insulation film;
- (d) forming a second wiring layer over said second insulation film;
- (e) removing said second insulation film within a first region surrounding said second wiring layer in plane, and using a bonding pad as a first wiring formed in said first region of said first wiring layer;
- (f) forming, over said bonding pad, a bump electrode electrically connected to said bonding pad;
- (g) after said step (f), cutting said semiconductor substrate along a division region to form individual semiconductor chips;
- (h) preparing an insulating tape, on a main surface of which a lead is formed, opposing a main surface of said semiconductor chip and said main surface of said insulation tape to each other, and disposing said semiconductor chip on said insulation tape so that said bump electrode is electrically connected to said lead;
- and
- (i) resin-scaling rear and side surfaces of said semiconductor chip so that said main surface of said semiconductor chip comes in no contact with a sealing resin under the condition that said semiconductor chip is disposed on said insulation tape.
Dependencies are inferred from the claim text.