Self-aligned method of forming a semiconductor memory array of floating gate memory cells with buried floating gate, pointed floating gate and pointed channel region, and a memory array made thereby

A method of forming an array of electrically programmable and erasable memory devices, comprising:

• forming spaced apart isolation regions on a semiconductor substrate that are substantially parallel to one another and extend in a first direction, with an active region between each pair of adjacent isolation regions, wherein the substrate has a surface and a first conductivity type;
• and
• forming a plurality of memory cells in each of the active regions, wherein the formation of each of the memory cells includes:
• forming a trench into a surface of a semiconductor substrate of a first conductivity type,
• forming first and second spaced-apart regions of a second conductivity type in the substrate with the first region formed underneath the trench, wherein a channel region is defined in the substrate between the first and second regions such that the channel region includes a first portion that extends substantially along a sidewall of the trench and a second portion that extends substantially along the substrate surface,
• forming an electrically conductive floating gate having lower and upper portions, wherein the lower portion is disposed in the trench adjacent to and insulated from the channel region first portion, and wherein the upper portion extends above the substrate surface and includes a lateral protrusion that extends in a direction substantially parallel to the substrate surface, and
• forming an electrically conductive control gate that is disposed over and insulated from the channel region second portion, and is disposed laterally adjacent to and insulated from the floating gate lateral protrusion.