Pocket implant for complementary bit disturb improvement and charging improvement of SONOS memory cell

A method of forming at least a portion of a SONOS dual bit memory core array upon a semiconductor substrate, the method comprising:

• forming a portion of a charge trapping dielectric layer over the substrate;
• forming a resist over the portion of the charge trapping dielectric layer
• patterning the resist to form a plurality of resist features having respective first spacings therebetween;
• performing a pocket implant through the first spacings and the portion of the charge trapping dielectric layer, the pocket implant performed at an angle relative to the semiconductor substrate so as to establish pocket implants within the substrate that extend at least partially under the resist features, wherein the pocket implant includes boron and is performed at an angle of between about 5 to 40 degrees relative to the substrate;
• performing a bitline implant through the first spacings and the portion of the charge trapping dielectric layer to establish buried bitlines within the substrate having a width corresponding generally to the first spacing, the bitlines not covering the portions of the pocket implants that extend under the resist features, wherein the bitline implant includes at least one of arsenic, phosphorous and antimony;
• removing the patterned resist;
• forming the remainder of the charge trapping dielectric layer over the portion of the charge trapping dielectric layer;
• forming a wordline material over the remainder of the charge trapping dielectric layer;
• and
• patterning the wordline material to form wordlines that overlie the bitlines.

A method of forming at least a portion of a SONOS dual bit memory core array upon a semiconductor substrate, the method comprising:

• forming a portion of a charge trapping dielectric layer over the substrate;
• forming a resist over the portion of the charge trapping dielectric layer
• patterning the resist to form a plurality of resist features having respective first spacings therebetween;
• performing a pocket implant through the first spacings and the portion of the charge trapping dielectric layer, the pocket implant performed at an angle relative to the semiconductor substrate so as to establish pocket implants within the substrate that extend at least partially under the resist features;
• performing a bitline implant through the first spacings and the portion of the charge trapping dielectric layer to establish buried bitlines within the substrate having a width corresponding generally to the first spacing, the bitlines not covering the portions of the pocket implants that extend under the resist features;
• removing the patterned resist;
• forming the remainder of the charge trapping dielectric layer over the portion of the charge trapping dielectric layer;
• forming a wordline material over the remainder of the charge trapping dielectric layer;
• patterning the wordline material to form wordlines that overlie the bitlines;
• and
• performing a threshold adjustment implant into the semiconductor substrate prior to forming the portion of the charge trapping dielectric layer.

A method of forming at least a portion of a SONOS dual bit memory core array upon a semiconductor substrate, the method comprising:

• forming pocket implants within the substrate without patterning a first insulating layer overlying the substrate or a charge trapping layer overlying the first insulating layer, the pocket implants being implanted at least partially under features formed out a resist material overlying the charge trapping layer and through the first insulating layer, the charge trapping layer and first spacings formed between the resist features;
• forming bitline implants through the first spacings to establish buried bitlines within the substrate having respective widths corresponding generally to the first spacings, the bitlines not covering the portions of the pocket implants that extend under the resist features, wherein the bitline implant is performed before the pocket implant;
• removing the resist features;
• forming a second insulating layer over the charge trapping layer;
• forming a wordline material over the second insulating layer;
• and
• patterning the wordline material to form wordlines that overlie the bitlines.