Methods of forming memory cell arrays

A method of forming an array of memory cells comprising:

• forming a series of capacitor constructions, the capacitor constructions having storage nodes;
• the capacitor constructions being defined to include a first set and a second set;
• forming an electrically conductive material over the capacitor constructions and in electrical connection with the storage nodes of the capacitor constructions;
• forming a first conductive line over the conductive material and in electrical connection with the first set of capacitor constructions through the conductive material;
• and
• forming a second conductive line over the first conductive line and in electrical connection with the second set of capacitor constructions through the conductive material;
• the second conductive line being electrically connected with the conductive material through conductive interconnects extending within openings in the first conductive line.

A method of forming an array of memory cells comprising:

• forming a series of capacitor constructions supported by a monocrystalline silicon substrate, the capacitor constructions having storage nodes;
• the capacitor constructions being defined to include a first set of capacitor constructions and a second set of capacitor constructions;
• the substrate having a damage region therein;
• after forming the capacitor constructions, breaking the substrate along the damage region;
• after breaking the substrate, forming a series of transistor gates over the capacitor constructions and in electrical connection with the capacitor constructions;
• the transistor gates being defined to include a first set that is in electrical connection with the storage nodes of the first set of capacitor constructions, and a second set that is in electrical connection with the storage nodes of the second set of capacitor constructions;
• forming a first conductive line over the transistor gates and in electrical connection with the first set of transistor gates;
• and
• forming a second conductive line over the first conductive line and in electrical connection with the second set of transistor gates.