Method and apparatus for performing low-density parity-check (LDPC) code operations using a multi-level permutation
AssigneeFlarion Technologies, Inc.
InventorTom Richardson
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AssigneeFlarion Technologies, Inc.
InventorTom Richardson
Estimating the term…
Methods and apparatus of the present invention can be used to implement a communications system wherein different devices using the same LDPC code can be implemented using different levels of parallelism. The use of a novel class of LDPC codes makes such differences in parallelism possible. Use of a factorable permuter in various embodiments of the invention make LDPC devices with different levels of parallelism in the encoder and decoder relatively easy to implement when using the codes in the class of LDPC codes discussed herein. The factorable permuter may be implemented as a controllable multi-stage switching devices which performs none, one, or multiple sequential reordering operations on a Z element vector passed between memory and a Z element vector processor, with the switching one individual vectors being controlled in accordance with the graph structure of the code being implemented.
A device for performing an LDPC processing operation, the device comprising:
A method of implementing an LDPC processing operation, said processing operation being one of an encoding and decoding operation, the method comprising:
Dependencies are inferred from the claim text.