Non-volatile memory and method with bit line compensation dependent on neighboring operating modes

A non-volatile memory comprising:

• an array of memory storage unit arranged in rows and columns;
• each memory storage unit having a charge storage unit, a control gate and a channel region defined by a source and a drain;
• a word line interconnecting the control gates of a page of memory storage units;
• a bit line for each memory storage unit of said page, said bit line switchably coupled to the drain thereof;
• a precharging circuit coupled to said bit line,
• said precharging circuit supplying a predetermined program inhibiting voltage to said bit line when the associated memory storage unit is slated for program inhibition and supplying a predetermined program enabling voltage said bit line when the associated memory storage unit is slated for programming, and
• said predetermined program enabling voltage having a predetermined offset that is a function of whether or not none, one, or both of neighboring memory storage units are in a program inhibit mode.

A non-volatile memory, comprising:

• an array of memory storage units, each unit having a charge storage unit between a control gate and a channel region defined by a source and a drain;
• a word line interconnecting the control gates of a page of memory storage units of said array;
• a bit line for each memory storage unit of the page, switchably coupled to the drain thereof;
• means for applying a first predetermined voltage to inhibit programming to each of the bit lines of those memory storage units of the page slated to be program inhibited;
• means for determining for each of those memory storage units of the page slated to be programmed whether or not its neighboring memory storage units are in a program inhibit mode;
• means for applying a second predetermined voltage to each bit line of those memory storage unit of the page slated to be programmed to enable programming, said second predetermined voltage for said each bit line being a function of the operation mode of its neighboring memory storage units so as to offset any perturbation therefrom;
• and
• means for applying a programming voltage pulse to said word line in order to program in parallel the memory storage units of the page, wherein those memory storage units having a bit line with said first predetermined voltage are program-inhibited by virtue of their floated channel boosted to a program inhibited voltage condition, and a perturbation resulted from the boosting on any neighboring programming memory storage unit is compensated by said offsetting from said second predetermined voltage.

A non-volatile memory, comprising:

• an array of memory storage units;
• a group of memory storage units among said array, each memory storage unit of the group having a bit line coupled thereto;
• a circuit for operating on said group of memory storage units in parallel while individual memory storage units of the group exist in one of a predetermined set of operation modes;
• and
• said circuit further comprising a voltage supply for supplying selected one of a predetermined set of voltages to each bit line;
• said selected voltage being a function of the operation modes of neighboring memory storage units.