Analog-to-digital converter for programmable logic
AssigneeAltera Corporation
InventorsTony San, Jinyan Zhang
Life of this patent
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Abstract
Digital-to-analog and analog-to-digital conversion are implemented in or using programmable logic. The DAC and ADC circuits may be hardwired in a programmable logic integrated circuit or may be implemented using an intellectual property (IP) core. The IP core would be a series of bits to configure the logic cells and other programmable logic of an integrated circuit to include one or more DACs or ADC, or both on the same integrated circuit. The DAC may be a sigma-delta-modulator-based implementation or a resistor-ladder-based implementation.
Claims18
A programmable logic integrated circuit comprising:
- a first DAC circuit providing a first analog output, wherein the first DAC is resistor-ladder based;
- a second DAC circuit providing a second analog output;
- a comparator circuit comprising inputs coupled to the first and second analog outputs of the first DAC circuit and the second DAC circuit;
- a calibration logic block coupled to a comparator output of the comparator circuit;
- and
- a memory having a memory data input coupled to the calibration logic block and a memory output coupled to an input of the first DAC circuit, wherein the memory data input comprises digital data comprising N bits and the memory output provides digital data having greater than N bits.
A method of operating a programmable logic integrated circuit comprising:
- configuring logic cells of the programmable logic integrated circuit to implement a first DAC and a second DAC, wherein the first DAC is resistor-ladder based;
- configuring a memory circuit to provide an M-bit output in response to an N-bit input, wherein M is greater than N;
- programmably coupling the output of the memory circuit to at least one of the first or second DAC circuits;
- and
- using the second DAC to calibrate the first DAC.
A programmable logic integrated circuit comprising:
- a first DAC circuit providing a first analog output, wherein the first DAC circuit is resistor-ladder based;
- a second DAC circuit providing a second analog output;
- a comparator circuit comprising inputs coupled to the first and second analog outputs of the first DAC circuit and the second DAC circuit;
- a calibration logic block coupled to a comparator output of the comparator circuit;
- and
- a memory having a memory data input coupled to the calibration logic block and a memory output coupled to an input of the first DAC circuit, wherein the memory data input comprises digital data comprising N bits and the memory output provides digital data having greater than N bits,
- wherein for a given input of N bits provided to the memory data input, the memory output of memory provides M bits output data, where M is greater than N.
Dependencies are inferred from the claim text.