Data amplifier having reduced data lines and/or higher data rates
AssigneeMicron Technology, Inc.
InventorsTodd A. Merritt, Donald M. Morgan
Life of this patent
Estimating the term…
Abstract
A data amplifier configured to allow for fewer data lines and/or increased processing speeds. Specifically, multiple helper flip-flops are used to prefetch data in a data amplifier. The helper flip-flops are configured to latch one or two of the data bits from a 4-bit prefetch in an alternating periodic fashion, thereby necessitating fewer data lines. Alternatively, the number of data lines can be maintained and faster bus processing speeds may be realized.
Claims20
A data amplifier comprising:
- a plurality of helper flip-flops configured to receive data;
- an isolation latch coupled to each of the plurality of helper flip-flops and configured to receive the data from each of the plurality of helper flip-flops;
- an inverter loop coupled to each isolation latch and configured to hold at least a portion of the data for a period of time;
- and
- an output driver coupled to each inverter loop and configured to transmit the at least a portion of data received from each inverter loop.
A data amplifier configured to receive data on a first data bus having a first bus width and configured to transmit data on a second bus having a second bus width, wherein the first bus width is greater than the second bus width, and wherein the data amplifier comprises a plurality of helper flip-flops configured to receive the data on the first bus and a plurality of logical devices configured to store, hold and deliver the data from the plurality of helper flip-flops onto the second bus in an alternating sequence.
A data amplifier configured to receive data on a first data bus having a first operating speed and configured to transmit data on a second bus having a second operating speed, wherein the second operating speed is greater than the first operating speed, and wherein the data amplifier comprises a plurality of helper flip-flops configured to receive the data on the first bus and a plurality of logical devices configured to store, hold and deliver the data from the plurality of helper flip-flops onto the second bus in an alternating sequence.
Dependencies are inferred from the claim text.