Cascade-connected ROM
AssigneeWinbond Electronics Corp.
InventorHwung-chung Chen
Life of this patent
Estimating the term…
Abstract
A serial read-only memory (SROM) device having an address range includes a memory array, an address clock pin for receiving an address clock signal, which starts an address cycle, a data clock pin for receiving a data clock signal, which starts a data cycle, a chip select/cascade (CS/CAS) pin for receiving a first control signal during the address cycle and for receiving a second control signal during the data cycle, a first data pin for receiving an address during the address cycle and for sending data during the data cycle, and a second data pin for receiving external data, the second data pin being connectable to the first data pin through a cascading data path defined therebetween, wherein the external data received at the second data pin may be transmitted to the first data pin when the cascading data path is connected.
Claims24
A serial read-only memory (SROM) device corresponding to an address range, comprising:
- a memory array;
- an address clock pin for receiving an address clock signal, wherein the address clock signal starts an address cycle;
- a data clock pin for receiving a data clock signal, wherein the data clock signal starts a data cycle;
- a chip select/cascade (CS/CAS) pin for receiving a first control signal during the address cycle and for receiving a second control signal during the data cycle;
- a first data pin for receiving an address during the address cycle and for outputting data during the data cycle;
- and
- a second data pin for receiving external data, the second data pin being connectable to the first data pin through a cascading data path defined therebetween, wherein the external data received at the second data pin may be transmitted to the first data pin when the cascading data path is connected.
A memory system, comprising:
- an address clock bus line for transmitting an address clock signal, wherein the address clock signal starts an address cycle;
- a data clock bus line for transmitting a data clock signal, wherein the data clock signal starts a data cycle;
- a data bus line for transmitting an address during the address cycle and data during the data cycle;
- a chip controller;
- and
- a plurality of serial read-only memory (SROM) chips each corresponding to a respective address range and including
- a memory array,
- an address clock pin coupled to the address clock bus line for receiving the address clock signal,
- a data clock pin coupled to the data clock bus line for receiving the data clock signal,
- a chip select/cascade (CS/CAS) pin coupled to the chip controller to receive a cascading signal during the address cycle and to receive a chip select signal during the data cycle,
- a first data pin for receiving the address during the address cycle and for outputting data during the data cycle, and
- a second data pin for receiving external data, the second data pin being connectable to the first data pin through a cascading data path defined therebetween, wherein the external data received at the second data pin may be transmitted to the first data pin when the cascading data path is connected.
Dependencies are inferred from the claim text.