US 6,947,482 B2Granted

System and method for high-speed decoding and ISI compensation in a multi-pair transceiver system

AssigneeBroadcom Corporation

InventorsOscar E. Azazzi, David Kruse, Arthur Abnous, Mehdi Hatamian

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Abstract

A method and a system for providing ISI compensation to an input signal in a bifurcated manner. ISI compensation is provided in two stages, a first stage compensates ISI components induced by characteristics of a transmitter's partial response pulse shaping filter, a second stage compensates ISI components induced by characteristics of a multi-pair transmission channel. First stage ISI compensation is performed in an inverse response filter having a characteristic feedback gain factor K, during system start-up. Second stage ISI compensation is performed by a single DFE in combination with a MDFE operating on tentative decisions output from a Viterbi decoder. As the DFE of the second stage reaches convergence, the feedback gain factor K of the first stage is ramped to zero.

Claims4

Dependent claims

A receiver for demodulating an analog signal transmitted by a remote transmitter over a transmission channel, the analog signal including a first ISI component induced by a characteristic of a pulse shaping filter included in the remote transmitter and a second ISI component induced by a characteristic of the transmission channel, the receiver comprising:

an analog front end, including an analog-to-digital converter, the analog front end receiving and converting the analog signal to a first digital signal;
an equalizer block coupled to the analog front end to receive the first digital signal, the equalizer block compensating the first ISI component in the first digital signal and outputting a second digital signal;
and
a decision feedback sequence estimation block, including an ISI compensation circuit, the ISI compensation circuit receiving the second digital signal outputted by the equalizer block and compensating the second ISI component in the second digital signal;
wherein the equalizer block comprises:
an ISI compensation filter having an impulse response substantially inverse of the impulse response of the pulse shaping filter of the remote transmitter, wherein the ISI compensation filter is an inverse partial response filter;
and
an adaptive gain stage.

5 more elements

Dependencies are inferred from the claim text.

Facts

Application: 09/858,760Filed 15 May 2001 · continuation
Priority: 9 Aug 1999
Published: US 2001/0019584 A16 Sep 2001
Granted: 20 Sep 2005
Term ends: Not estimatedThe source records don’t support an estimate.

Classification40 codes

H04L 7/0062
Detection of the synchronisation error by features other than the received signal transition: detection of error based on data decision error,…
G01R 31/3004
Marginal testing, e.g. by varying supply voltage: current or voltage test
G01R 31/3008
Current or voltage test: quiescent current [IDDQ] test or leakage current test
G01R 31/3016
Marginal testing, e.g. by varying supply voltage: delay or race condition test, e.g. race hazard test