Methods for packaging microelectronic devices

A method for packaging microelectronic devices, comprising:

• providing a plurality of singulated microelectronic dies;
• coupling the plurality of individual microelectronic dies to a support member;
• covering the dies and at least a portion of the support member with a dielectric layer;
• forming a plurality of vias through the dielectric layer between the dies;
• fabricating a plurality of conductive links in corresponding vias;
• and
• removing the support member from the dies and the dielectric layer.

A method for packaging microelectronic devices, comprising:

• providing a plurality of singulated microelectronic dies;
• coupling the plurality of individual microelectronic dies to a support member;
• covering the dies and at least a portion of the support member with a dielectric layer;
• forming a plurality of vias through the dielectric layer between the dies;
• fabricating a plurality of conductive links in corresponding vias;
• and
• forming a plurality of pads in and/or on the support member, the pads being electrically coupled to and not aligned with corresponding conductive links.

A method for manufacturing microelectronic devices, comprising:

• constructing a plurality of microelectronic dies on a microelectronic workpiece, the dies having a first side with bond-pads, a second side opposite the first side, and an integrated circuit;
• cutting the microelectronic workpiece to separate the dies;
• attaching individual dies to a support member with the second side facing the support member;
• depositing a dielectric layer over the dies and at least a portion of the support member, the dielectric layer having a first surface and a second surface opposite the first surface;
• forming a plurality of vias in the dielectric layer between the dies, the vias extending from the first surface to the second surface;
• and
• fabricating a plurality of conductive links in corresponding vias, at least some of the conductive links being electrically coupled to corresponding dies.

A method for manufacturing microelectronic devices including microelectronic dies having an integrated circuit, a first side with bond-pads electrically coupled to the integrated circuit, and a second side opposite the first side, the method comprising:

• constructing a plurality of dies on a microelectronic workpiece;
• cutting the microelectronic workpiece to separate the dies;
• coupling the dies to a support member;
• covering the dies and at least a portion of the support member with a dielectric layer;
• forming a plurality of vias in the dielectric layer that extend through the dielectric layer;
• forming a plurality of apertures in the support member that are aligned with corresponding vias;
• forming a first plurality of conductive links in corresponding vias;
• and
• forming a second plurality of conductive links in corresponding apertures that are electrically coupled to corresponding first conductive links.

A method for manufacturing microelectronic devices including microelectronic dies having an integrated circuit and bond-pads electrically coupled to the integrated circuit, the method comprising:

• forming a plurality of dies on a microelectronic workpiece, wherein the dies are spaced apart by a first distance;
• cutting the microelectronic workpiece to separate the dies;
• attaching the dies to a first side of a support member in an arrangement in which the dies are spaced apart by a second distance greater than the first distance;
• depositing a dielectric layer over the dies and at least a portion of the first side of the support member without depositing the dielectric layer over a second side of the support member opposite the first side;
• forming a plurality of vias through the dielectric layer between the dies, the vias being spaced apart from the dies;
• and
• constructing a plurality of conductive links in corresponding vias.

A method for manufacturing microelectronic devices including microelectronic dies having an integrated circuit and bond-pads electrically coupled to the integrated circuit, the method comprising:

• forming a plurality of dies on a microelectronic workpiece, wherein the dies are spaced apart by a first distance;
• cutting the microelectronic workpiece to separate the dies;
• attaching the dies to a support member in an arrangement in which the dies are spaced apart by a second distance greater than the first distance;
• depositing a dielectric layer over the dies and at least a portion of the support member;
• forming a plurality of vias through the dielectric layer between the dies, the vias being spaced apart from the dies;
• constructing a plurality of conductive links in corresponding vias;
• and
• removing the support member from the dies and the dielectric layer.

A method for manufacturing microelectronic devices including microelectronic dies having an integrated circuit and bond-pads electrically coupled to the integrated circuit, the method comprising:

• forming a plurality of dies on a microelectronic workpiece, wherein the dies are spaced apart by a first distance;
• culling the microelectronic workpiece to separate the dies;
• attaching the dies to a support member in an arrangement in which the dies are spaced apart by a second distance greater than the first distance;
• depositing a dielectric layer over the dies and at least a portion of the support member;
• forming a plurality of vias through the dielectric layer between the dies, the vias being spaced apart from the dies;
• constructing a plurality of conductive links in corresponding vias;
• and
• forming a plurality of pads in and/or on the support member, the pads being electrically coupled to and not aligned with corresponding conductive links.

A method for packaging microelectronic devices including microelectronic dies having a first side with bond-pads and a second side opposite the first side, the method comprising:

• coupling a first die and a second die to a support member with the second sides facing the support member;
• depositing a dielectric layer over the first and second dies and at least a portion of the support member, the dielectric layer having a first surface and a second surface opposite the first surface;
• forming a first via and a second via from the first surface of the dielectric layer to the second surface between the first and second dies;
• fabricating a first conductive link in the first via and a second conductive link in the second via, wherein the first conductive link is electrically coupled to the first die and the second conductive link is electrically coupled to the second die;
• and
• forming a first ball-pad array and a second ball-pad array in and/or on the dielectric layer, wherein the first ball-pad array is electrically coupled to the first die and the second ball-pad array is electrically coupled to the second die.

A method for stacking microelectronic devices, comprising:

• providing a first microelectronic device having a first dielectric substrate, a first microelectronic die attached to the first dielectric substrate, a first dielectric layer over the first die, and a first plurality of conductive links extending through the first dielectric layer and the first dielectric substrate;
• providing a second microelectronic device having a second dielectric substrate, a second microelectronic die attached to the second dielectric substrate, a second dielectric layer over the second die, and a second plurality of conductive links extending through the second dielectric layer and the second dielectric substrate;
• and
• stacking the second microelectronic device on top of the first microelectronic device with the first plurality of conductive links aligned with and electrically coupled to corresponding conductive links in the second plurality of conductive links.